Display panel and electronic terminal

1 . A display panel, comprising:

a display area and a non-display area disposed on at least one side of the display area;

a plurality of data lines disposed in the display area, the data lines comprising a first data line and a second data line, wherein a length of the first data line is greater than a length of the second data line;

a plurality of source lines disposed in the non-display area; and

a plurality of demultiplexers disposed in the non-display area and connected between the source lines and the data lines, wherein each of the demultiplexers comprises multiple transistors;

wherein each of the transistors comprises a drain and a gate; the transistors comprise a first transistor connected to the first data line, and a second transistor connected to the second data line, a first rated capacitance is formed between the first data line and the gate of the first transistor, a second rated capacitance is formed between the second data line and the gate of the second transistor, and the first rated capacitance is higher than the second rated capacitance;

wherein an overlapping area of the drain and the gate of the first transistor in an area where the gate and the drain of the first transistor are arranged face to face is greater than an overlapping area of the drain and the gate of the second transistor in an area where the gate and the drain of the second transistor are arranged face to face;

wherein each of the first transistor and the second transistor comprises an active portion; in each of the first transistor and the second transistor, the gate is disposed on one side of the active portion, and the drain is disposed on one side of the gate away from the active portion; the drain comprises a first portion and a second portion, and the second portion is connected between the first portion and the active portion;

wherein an area of an orthographic projection of the gate of the first transistor projected on the corresponding second portion is larger than an area of an orthographic projection of the gate of the second transistor projected on the corresponding second portion; and

wherein a thickness of the gate of the first transistor is greater than a thickness of the gate of the second transistor.

2 . The display panel according to claim 1 , wherein the display panel comprises a substrate; in each of the transistors, the gate is located on one side of the active portion away from the substrate; and a spacing between the gate and the drain of the first transistor in a direction from the gate of the first transistor to the corresponding second portion is less than a spacing between the gate and the drain of the second transistor in a direction from the gate of the second transistor to the corresponding second portion.

3 . The display panel according to claim 1 , wherein the display panel comprises a substrate; in each of the transistors, the gate is located on one side of the active portion close to the substrate; and the overlapping area of the drain and the gate of the first transistor is larger than the overlapping area of the drain and the gate of the second transistor.

4 . The display panel according to claim 3 , wherein a size of an orthographic projection of the drain of the first transistor projected on the gate in a direction from the gate of the first transistor to the corresponding second portion is larger than a size of an orthographic projection of the drain of the second transistor projected on the gate in a direction from the gate of the second transistor to the corresponding second portion.

5 . The display panel according to claim 3 , further comprising:

a gate insulating layer disposed between the gates and the drains of the transistors, comprising a first gate insulating portion disposed between the drain and the gate of the first transistor and comprising a second gate insulating portion disposed between the drain and the gate of the second transistor;

wherein a thickness of the first gate insulating portion is less than a thickness of the second gate insulating portion.

6 . The display panel according to claim 2 , wherein a width of the gate of the first transistor is equal to a width of the gate of the second transistor.

7 . The display panel according to claim 1 , wherein in each of the transistors, a thickness of the drain is greater than a thickness of the gate.

8 . The display panel according to claim 2 , wherein in a direction perpendicular to a cross section of the display panel, a dimension of the drain of the first transistor is greater than a dimension of the drain of the second transistor.

9 . The display panel according to claim 8 , wherein a thickness of the drain of the first transistor is greater than a thickness of the drain of the second transistor.

10 . The display panel according to claim 1 , wherein in a horizontal direction of a cross section of the display panel, a distance between the gate and the drain of the first transistor is less than a distance between the gate and the drain of the second transistor.

11 . The display panel according to claim 1 , wherein each of the transistors further comprises a channel portion and two doped portions disposed at two sides of the channel portion, wherein each doped portion comprises a heavily doped portion and a lightly doped portion disposed between the heavily doped portion and the channel portion, and a concentration of dopants in the heavily doped portion is greater than a concentration of dopants in the lightly doped portion.

12 . An electronic terminal, comprising a display panel, the display panel comprising:

a display area and a non-display area disposed on at least one side of the display area;

a plurality of data lines disposed in the display area, the data lines comprising a first data line and a second data line, wherein a length of the first data line is greater than a length of the second data line;

a plurality of source lines disposed in the non-display area; and

a plurality of demultiplexers disposed in the non-display area and connected between the source lines and the data lines, wherein each of the demultiplexers comprises multiple transistors;

wherein each of the transistors comprises a drain and a gate; the transistors comprise a first transistor connected to the first data line, and a second transistor connected to the second data line, a first rated capacitance is formed between the first data line and the gate of the first transistor, a second rated capacitance is formed between the second data line and the gate of the second transistor, and the first rated capacitance is higher than the second rated capacitance;

wherein an overlapping area of the drain and the gate of the first transistor in an area where the gate and the drain of the first transistor are arranged face to face is greater than an overlapping area of the drain and the gate of the second transistor in an area where the gate and the drain of the second transistor are arranged face to face;

wherein each of the first transistor and the second transistor comprises an active portion; in each of the first transistor and the second transistor, the gate is disposed on one side of the active portion, and the drain is disposed on one side of the gate away from the active portion; the drain comprises a first portion and a second portion, and the second portion is connected between the first portion and the active portion;

wherein an area of an orthographic projection of the gate of the first transistor projected on the corresponding second portion is larger than an area of an orthographic projection of the gate of the second transistor projected on the corresponding second portion; and

wherein a thickness of the gate of the first transistor is greater than a thickness of the gate of the second transistor.