Array substrate, display panel and display device
The present disclosure provides an array substrate including a plurality of pixel units, at least one of the pixel units includes a first pixel sub-unit, the first pixel sub-unit includes a first transistor, a second transistor, and a first pixel electrode; the first transistor includes a first active pattern, the second transistor including a second active pattern, the first active pattern includes a first channel region, the second active pattern includes a second channel region; at least one division pattern is arranged between a third electrode and a fourth electrode, and an orthographic projection of the division pattern on a first base substrate is partially overlapped with an orthographic projection of the second channel region on the first base substrate.
1 . An array substrate, comprising: a first base substrate, wherein a plurality of gate lines, a plurality of data lines and a plurality of discharging lines are arranged on the first base substrate, the gate lines extend along a first direction, the data lines and the discharging lines extend along a second direction, the gate lines and the data lines define a plurality of pixel units, and at least one of the pixel units includes a first pixel sub-unit, the first pixel sub-unit comprises a first transistor, a second transistor, and a first pixel electrode;
the first transistor comprises a first gate electrode, a first active pattern, a first electrode and a second electrode, wherein the first gate electrode is connected with one of the gate lines corresponding thereto, the first electrode is connected with one of the data lines corresponding thereto, and the second electrode is connected with the first pixel electrode;
the second transistor comprises a second gate electrode, a second active pattern, a third electrode and a fourth electrode, wherein the second gate electrode is connected with the one of the gate lines, the third electrode is connected with one of the discharging lines corresponding thereto, the fourth electrode is connected with the first pixel electrode, and the second active pattern comprises a second channel region located between the third electrode and the fourth electrode; and
at least one division pattern is arranged between the third electrode and the fourth electrode, and an orthographic projection of the division pattern on the first base substrate is partially overlapped with an orthographic projection of the second channel region on the first base substrate.
2 . The array substrate of claim 1 , wherein the division pattern comprises a first portion and a second portion connected to each other, an orthographic projection of the first portion on the first base substrate is located in a region where an orthographic projection of the second channel region on the first base substrate is located, and an orthographic projection of the second portion on the first base substrate does not overlap with the orthographic projection of the second channel region on the first base substrate.
3 . The array substrate of claim 1 , wherein the first active pattern comprises a first channel region between the first electrode and the second electrode, the first channel region having a length of L1; and
a distance, in a length direction of the second channel region, between any two of the third electrode, the fourth electrode, and the division pattern adjacent to each other in the length direction of the second channel region ranges from ½×L1 to 3/2×L1.
4 . The array substrate of claim 1 , wherein a ratio of a dimension of a width of the division pattern in a length direction of the second channel region to a dimension of a width of the fourth electrode in the length direction of the second channel region ranges from 1 to 2.
5 . The array substrate of claim 4 , wherein the dimension of the width of the division pattern in the length direction of the second channel region ranges from 2.5 μm to 3.5 μm.
6 . The array substrate of claim 1 , wherein a material of the division pattern comprises a conductive material;
the division pattern extends in a width direction of the second channel region; and
a shape of an orthographic projection of the division pattern on the first base substrate is a rectangle, an ellipse, or an octagon.
7 . The array substrate of claim 1 , wherein the division pattern comprises at least two division sub-patterns arranged at intervals along a width direction of the second channel region, wherein the interval between any two adjacent division sub-patterns is less than or equal to 1.5 μm.
8 . The array substrate of claim 1 , wherein two or more division patterns are provided, a connection pattern is provided between two adjacent division patterns, two ends of the connection pattern connect the two adjacent division patterns respectively, and an orthographic projection of the connection pattern on the first base substrate does not overlap the orthographic projection of the second channel region on the first base substrate.
9 . The array substrate of claim 1 , wherein an orthographic projection of the second active pattern on the first base substrate covers an orthographic projection of the division pattern on the first base substrate, and
a distance between an outer edge of the division pattern and an outer edge, which is on the same side as the outer edge of the division pattern, of the second active pattern ranges from 1 μm to 2 μm.
10 . The array substrate of claim 1 , wherein the first active pattern comprises a first channel region between the first electrode and the second electrode, the first channel region having a length of L1 and a width of W1;
the second channel region has a length of L2 and a width of W2; and
W1, L1, W2 and L2 satisfy following conditions: W2/L2 is not greater than W1/L1, and L2 is not less than 3/2×L1.
11 . The array substrate of claim 1 , wherein the division pattern is provided in the same layer as the third electrode and the fourth electrode;
the third electrode, the fourth electrode and the division pattern each extend along the second direction, and the third electrode, the division pattern and the fourth electrode are arranged along the first direction.
12 . The array substrate of claim 11 , wherein the third electrode and the discharging line are of a unitary structure.
13 . The array substrate of claim 1 , wherein the pixel unit further comprises a second pixel sub-unit, the second pixel sub-unit comprises a third transistor and a second pixel electrode;
the third transistor comprises a third gate, a third active pattern, a fifth electrode and a sixth electrode, wherein the third gate is connected with one of the gate lines, the fifth electrode is connected with one of the data lines, and the sixth electrode is connected with the second pixel electrode;
the third active pattern comprises a third channel region between the fifth electrode and the sixth electrode, the third channel region has a length of L3 and a width of W3;
the first active pattern comprises a first channel region between the first electrode and the second electrode, the first channel region has a length of L1 and a width of W1;
wherein, W3=W1, and L3=L1.
14 . The array substrate of claim 13 , wherein
the first pixel electrode and the second pixel electrode are arranged along the second direction, and the gate line, the first transistor, the second transistor and the third transistor are all located between the first pixel electrode and the second pixel electrode;
the first transistor and the second transistor are both located between the data line and the discharging line, and wherein
the first transistor and the third transistor are arranged along the second direction; and
the first transistor and the second transistor are arranged along the first direction.
15 . The array substrate of claim 14 , wherein the first electrode and the second electrode each extend along the first direction, and first electrode and the second electrode are arranged along the second direction;
the fifth electrode and the sixth electrode each extend along the first direction, and the fifth electrode and the sixth electrode are arranged along the second direction; and
the first electrode and the fifth electrode are the same.
16 . The array substrate of claim 15 , wherein the first active pattern and the third active pattern are connected as a unitary structure;
or, the first active pattern and the third active pattern are arranged at intervals.
17 . The array substrate of claim 13 , wherein the first transistor, the third transistor, and the second transistor are all arranged along the first direction; and wherein
the first electrode and the second electrode each extend along the second direction, and the first electrode a the second electrode are arranged along the first direction;
the fifth electrode and sixth electrode each extend along the second direction, and the fifth electrode and the sixth electrode are arranged along the first direction; and
the first electrode and the fifth electrode are the same;
the third electrode, the fourth electrode and the division pattem all extend along the second direction, and the third electrode, the division pattern and the fourth electrode are arranged along the first direction; and
the second electrode and the fourth electrode are the same.
18 . The array substrate of claim 17 , wherein the first active pattern, the second active pattern, and the third active pattern are connected as a unitary structure, and wherein
the first pixel electrode and the second pixel electrode are both rectangular electrodes;
or, the first pixel electrode and the second pixel electrode are both in a shape of a Chinese character ‘ ’.
19 . A display panel, comprising: an array substrate, and an opposite substrate arranged opposite to the array substrate, wherein the array substrate adopts the array substrate of claim 1 .
20 . A display device, comprising: the display panel of claim 19 .