Array substrate and display panel including the same
View Patent ↗The present disclosure relates to an array substrate and a display panel, the array substrate including at least one pixel unit and a first gate line, each pixel unit including at least one sub-pixel, each sub-pixel including a pixel circuit, the pixel circuit including a first transistor, the first gate line being electrically connected to a gate of the first transistor through a first connecting part, the first connecting part and the first gate line being located in different conductive layers from each other. The array substrate provided in some embodiments of the present disclosure eliminates the risk of pixel circuit transistor damage caused by electrostatic conduction of the gate line by means of the measure of same layer separation and cross layer connection of the gate of the transistor and the corresponding gate line.
1 . An array substrate, comprising:
at least one pixel unit, each pixel unit comprising at least one sub-pixel, each sub-pixel comprising a pixel circuit, the pixel circuit comprising a first transistor; and
a first gate line electrically connected to a gate of the first transistor through a first connecting part, wherein the first connecting part and the first gate line are in different conductive layers from each other,
wherein the array substrate comprises a buffer layer and a light shielding layer, the buffer layer is above a base substrate of the array substrate and the light shielding layer is between the buffer layer and the base substrate, the light shielding layer comprises a light shielding pattern made of a conductive material, and the light shielding pattern is electrically connected to a source-drain of the first transistor through a third via, wherein the third via is arranged on an interlayer dielectric layer and the buffer layer,
wherein the first connecting part comprises: a first connecting sub-part and a second connecting sub-part arranged in a same layer as the source-drain of the first transistor, and a third connecting sub-part arranged in a same layer as the light shielding layer, and
wherein the first connecting sub-part is electrically connected to the gate of the first transistor through a fourth via, the second connecting sub-part is electrically connected to the first gate line through a fifth via, and the third connecting sub-part is electrically connected to the first connecting sub-part and the second connecting sub-part respectively through the third via, wherein the fourth via and the fifth via are arranged on the interlayer dielectric layer.
2 . The array substrate according to claim 1 , wherein the third via comprises a first sub-via arranged on the interlayer dielectric layer and a second sub-via arranged on the buffer layer, orthogonal projections of the first sub-via and the second sub-via on the base substrate of the array substrate at least partially overlap with each other.
3 . The array substrate according to claim 1 , wherein the pixel circuit further comprises a second transistor, and the array substrate further comprises:
a second gate line electrically connected to a gate of the second transistor, the second gate line comprising a first sub gate line and a second sub gate line separated from each other, the first sub gate line and the second sub gate line are electrically connected to each other through a second connecting part, wherein the second connecting part and the second gate line are in different conductive layers from each other.
4 . The array substrate according to claim 3 , wherein at least a portion of the second connecting part is arranged in a same layer as a source-drain of the second transistor.
5 . The array substrate according to claim 4 , wherein the second connecting part is electrically connected to the first sub gate line and the second sub gate line through a seventh via and an eighth via respectively, the seventh via and the eighth via are arranged on the interlayer dielectric layer.
6 . The array substrate according to claim 4 , wherein the second connecting part comprises: a fourth connecting sub-part and a fifth connecting sub-part arranged in the same layer as the source-drain of the second transistor, as well as a sixth connecting sub-part arranged in the same layer as the light shielding layer, and
wherein the fourth connecting sub-part is electrically connected to the first sub gate line through a ninth via, the fifth connecting sub-part is electrically connected to the second sub gate line through a tenth via, the sixth connecting sub-part is electrically connected to the fourth connecting sub-part and the fifth connecting sub-part respectively through an eleventh via, the ninth via and the tenth via are arranged on the interlayer dielectric layer, and the eleventh via is arranged on the interlayer dielectric layer and the buffer layer.
7 . The array substrate according to claim 6 , wherein the eleventh via comprises a third sub-via arranged on the interlayer dielectric layer and a fourth sub-via arranged on the buffer layer, orthogonal projections of the third sub-via and the fourth sub-via on the base substrate of the array substrate at least partially overlap with each other.
8 . The array substrate according to claim 3 , wherein the first sub gate line and the second sub gate line are separated from each other between two adjacent sub-pixels in the pixel unit.
9 . The array substrate according to claim 3 , wherein the pixel circuit comprises a 3T1C pixel circuit, wherein at least one of the first transistor and the second transistor is a switch transistor.
10 . The array substrate according to claim 3 , wherein at least one of the first transistor and the second transistor is a thin film transistor.
11 . A display panel comprising the array substrate according to claim 1 .