Integrated circuit device and method of manufacturing
View Patent ↗An integrated circuit (IC) device includes a substrate, first and second semiconductor devices correspondingly in different first and second doped regions in the substrate. A gate of the first semiconductor device is electrically coupled to a source/drain of the second semiconductor device. The IC device further includes a first protection device configured as one of a first forward diode and a first reverse diode, and a second protection device configured as the other of the first forward diode and the first reverse diode. The first forward diode and the first reverse diode are electrically coupled in series between the substrate and a doped well. The doped well is in the first doped region and a source/drain of the first semiconductor device is in the doped well. Alternatively, the doped well is in the second doped region, and the source/drain of the second semiconductor device is in the doped well.
1 . An integrated circuit (IC) device, comprising:
a substrate;
a first semiconductor device in a first doped region in the substrate;
a second semiconductor device in a second doped region in the substrate, wherein
the first doped region and the second doped region are different from each other, and
a gate of the first semiconductor device is electrically coupled to a source/drain of the second semiconductor device;
a first protection device configured as one of a first forward diode and a first reverse diode; and
a second protection device configured as the other of the first forward diode and the first reverse diode, the first forward diode and the first reverse diode electrically coupled in series between the substrate and a doped well, wherein
the doped well is in the first doped region, and a source/drain of the first semiconductor device is in the doped well, or
the doped well is in the second doped region, and the source/drain of the second semiconductor device is in the doped well.
2 . The IC device of claim 1 , wherein
each of the first protection device and the second protection device comprises at least one of:
a P-type diode,
an N-type diode,
a diode-connected metal-oxide semiconductor (MOS) transistor, or
a diode-connected bipolar junction transistor (BJT).
3 . The IC device of claim 1 , wherein
the doped well is configured to receive a voltage higher than a voltage of the substrate, and
one of
the first protection device comprises a P-type diode having an anode electrically coupled to the doped well, and the second protection device comprises an N-type diode having an anode electrically coupled to the substrate,
the first protection device comprises a diode-connected P-channel metal-oxide semiconductor (PMOS) transistor electrically coupled to the doped well, and the second protection device comprises a diode-connected N-channel metal-oxide semiconductor (NMOS) transistor electrically coupled to the substrate, or
the first protection device comprises a diode-connected PNP bipolar junction transistor (BJT), and the second protection device comprises a diode-connected NPN BJT.
4 . The IC device of claim 1 , wherein
the doped well is configured to receive a voltage higher than a voltage of the substrate, and
one of
the first protection device comprises a diode-connected P-channel metal-oxide semiconductor (PMOS) transistor electrically coupled to the doped well, and the second protection device comprises a diode having a cathode electrically coupled to the substrate,
the first protection device comprises a diode having an anode electrically coupled to the doped well, and the second protection device comprises a diode-connected N-channel metal-oxide semiconductor (NMOS) transistor electrically coupled to the substrate,
the first protection device comprises a diode having a cathode electrically coupled to the doped well, and the second protection device comprises a diode-connected PMOS transistor electrically coupled to the substrate, or
the first protection device comprises a diode-connected NMOS transistor electrically coupled to the doped well, and the second protection device comprises a diode having an anode electrically coupled to the substrate.
5 . The IC device of claim 1 , wherein
the doped well is configured to receive a voltage higher than a voltage of the substrate, and
one of
the first protection device comprises a diode-connected P-channel metal-oxide semiconductor (PMOS) transistor electrically coupled to the doped well, and the second protection device comprises a diode-connected NPN bipolar junction transistor (BJT) electrically coupled to the substrate, or
the first protection device comprises a diode-connected PNP BJT electrically coupled to the doped well, and the second protection device comprises a diode-connected N-channel metal-oxide semiconductor (NMOS) transistor electrically coupled to the substrate.
6 . The IC device of claim 1 , wherein
the doped well is configured to receive a voltage lower than a voltage of the substrate, and
one of
the first protection device comprises an N-type diode having an anode electrically coupled to the doped well, and the second protection device comprises a P-type diode having an anode electrically coupled to the substrate,
the first protection device comprises a diode-connected N-channel metal-oxide semiconductor (NMOS) transistor electrically coupled to the doped well, and the second protection device comprises a diode-connected P-channel metal-oxide semiconductor (PMOS) transistor electrically coupled to the substrate, or
the first protection device comprises a diode-connected NPN bipolar junction transistor (BJT), and the second protection device comprises a diode-connected PNP BJT.
7 . The IC device of claim 1 , wherein
the doped well is configured to receive a voltage lower than a voltage of the substrate, and
one of
the first protection device comprises a diode electrically coupled to the doped well, and the second protection device comprises a diode-connected NPN bipolar junction transistor (BJT) electrically coupled to the substrate, or
the first protection device comprises a diode-connected PNP BJT electrically coupled to the doped well, and the second protection device comprises a diode electrically coupled to the substrate.
8 . The IC device of claim 1 , wherein
the doped well is configured to receive a voltage lower than a voltage of the substrate, and
one of
the first protection device comprises a diode-connected NPN bipolar junction transistor (BJT) electrically coupled to the doped well, and the second protection device comprises a diode-connected P-channel metal-oxide semiconductor (PMOS) transistor electrically coupled to the substrate, or
the first protection device comprises a diode-connected N-channel metal-oxide semiconductor (NMOS) transistor electrically coupled to the doped well, and the second protection device comprises a diode-connected PNP BJT electrically coupled to the substrate.
9 . The IC device of claim 1 , wherein
both of the first protection device and the second protection device are:
P-type diodes,
N-type diodes,
diode-connected N-channel metal-oxide semiconductor (NMOS) transistors,
diode-connected P-channel metal-oxide semiconductor (PMOS) transistors,
diode-connected NPN bipolar junction transistors (BJTs), or
diode-connected PNP BJTs.
10 . The IC device of claim 1 , wherein
the doped well is a first doped well in the second doped region,
the second doped region further comprises a second doped well having a conductivity opposite to the first doped well,
the gate of the first semiconductor device is electrically coupled to the second doped well, and
the IC device further comprises:
a second forward diode; and
a second reverse diode, the second forward diode and the second reverse diode electrically coupled in series between the substrate and the second doped well.
11 . The IC device of claim 1 , wherein
the doped well is a first doped well in the first doped region,
the first doped region further comprises a second doped well having a conductivity opposite to the first doped well, and
the IC device further comprises:
a third semiconductor device having a gate electrically coupled to the gate of the first semiconductor device;
a second forward diode; and
a second reverse diode, the second forward diode and the second reverse diode electrically coupled in series between the substrate and the second doped well.
12 . The IC device of claim 11 , wherein
the second doped region further comprises a third doped well, the source/drain of the second semiconductor device is in the third doped well, and
the IC device further comprises:
a third forward diode; and
a third reverse diode, the third forward diode and the third reverse diode electrically coupled in series between the substrate and the third doped well.
13 . The IC device of claim 12 , wherein
the second doped region further comprises a fourth doped well having a conductivity opposite to the third doped well,
the gates of the first and third semiconductor devices are electrically coupled to the fourth doped well, and
the IC device further comprises:
a fourth forward diode; and
a fourth reverse diode, the fourth forward diode and the fourth reverse diode electrically coupled in series between the substrate and the fourth doped well.
14 . The IC device of claim 13 , wherein
one of the first doped well and the second doped well is a first P-well,
one of the third doped well and the fourth doped well is a second P-well, and
the IC device further comprises:
a first diode having an anode electrically coupled to the first P-well, and a cathode electrically coupled to the second P-well; and
a second diode having an anode electrically coupled to the second P-well, and a cathode electrically coupled to the first P-well.
15 . The IC device of claim 11 , wherein
one of the first doped well and the second doped well is a P-well,
the other of the first doped well and the second doped well is an N-well, and
the IC device further comprises, in the first doped region, at least one of:
a grounded-gate N-channel metal-oxide semiconductor (ggNMOS) transistor electrically coupled between the P-well and the gates of the first and third semiconductor devices, or
a gate-VDD P-channel metal-oxide semiconductor (gdPMOS) transistor electrically coupled between the N-well and the gates of the first and third semiconductor devices.
16 . An integrated circuit (IC) device, comprising:
a substrate;
a first semiconductor device in a first doped region in the substrate;
a second semiconductor device in a second doped region in the substrate, wherein
the first doped region and the second doped region are different from each other, and
a gate of the first semiconductor device is electrically coupled to a source/drain of the second semiconductor device;
a first protection device and a second protection device electrically coupled in series between the substrate and a doped well, wherein
the doped well is in the first doped region, and a source/drain of the first semiconductor device is in the doped well, or
the doped well is in the second doped region, and the source/drain of the second semiconductor device is in the doped well;
a first electrical connection electrically coupling the first protection device to the doped well;
a second electrical connection electrically coupling the second protection device to the substrate; and
a third electrical connection electrically coupling the gate of the first semiconductor device to the source/drain of the second semiconductor device,
wherein the first electrical connection and the second electrical connection are below a highest metal layer containing a conductive pattern of the third electrical connection,
the first protection device is configured as one of a first forward diode and a first reverse diode, and
the second protection device is configured as the other of the first forward diode and the first reverse diode.
17 . The IC device of claim 16 , wherein the doped well is a first doped well in the first doped region, the IC device further comprising:
a second doped well in the second doped region, wherein the source/drain of the second semiconductor device is in the second doped well;
a third protection device and a fourth protection device electrically coupled in series between the substrate and the second doped well;
a fourth electrical connection electrically coupling the third protection device to the second doped well; and
a fifth electrical connection electrically coupling the fourth protection device to the substrate,
wherein the fourth electrical connection and the fifth electrical connection are below the highest metal layer containing the conductive pattern of the third electrical connection.
18 . The IC device of claim 16 , wherein the doped well is a first doped well in the second doped region, the IC device further comprising:
a second doped well in the first doped region, wherein the source/drain of the first semiconductor device is in the second doped well;
a third protection device and a fourth protection device electrically coupled in series between the substrate and the second doped well;
a fourth electrical connection electrically coupling the third protection device to the second doped well; and
a fifth electrical connection electrically coupling the fourth protection device to the substrate,
wherein the fourth electrical connection and the fifth electrical connection are below the highest metal layer containing the conductive pattern of the third electrical connection.
19 . The IC device of claim 16 , wherein
one of the first protection device and the second protection device is configured to discharge, by a leakage current, electric charges from the doped well to the substrate, and
the other of the first protection device and the second protection device is configured to sustain a working voltage applied across the doped well and the substrate in operation of the IC device.
20 . An integrated circuit (IC) device, comprising:
a substrate;
a first doped well in a first doped region in the substrate;
a second doped well in a second doped region in the substrate;
a first protection device comprising a first P-N junction, and configured as one of a first forward diode and a first reverse diode;
a second protection device comprising a second P-N junction, and configured as the other of the first forward diode and the first reverse diode, the first forward diode and the first reverse diode electrically coupled in series between the substrate and a doped well which is one of the first and second doped wells;
a first gate over the first doped well; and
a second gate over the second doped well,
wherein
P-type regions of the first and second P—N junctions are electrically coupled to each other, or N-type regions of the first and second P—N junctions are electrically coupled to each other, and
the first gate is electrically coupled over the first doped well to the second doped well.