Solid-state imaging element and method of manufacturing same
Provided is a solid-state imaging element including pixels, a substrate on which the pixels are provided, a first transistor, in the pixels, that includes a first gate electrode portion, a first gate insulating film provided between an active region of the substrate in which a channel of the first transistor is formed and a first side surface of the first gate electrode portion facing the active region, and a first insulating film on a second side surface of the first gate electrode portion other than the first side surface and thicker than the first gate insulating film, in which a depth of the first insulating film is the same as or deeper than a depth of the first gate electrode portion, and a width of an upper surface of the first gate electrode portion is wider than a width of a bottom surface of the first gate electrode portion.
1 . A solid-state imaging element comprising:
a substrate;
a plurality of pixels on the substrate, wherein the plurality of pixels is configured to photoelectrically convert incident light;
a transistor in each of the plurality of pixels, wherein
the transistor includes a first gate electrode portion, a second gate electrode portion, and a third gate electrode portion,
the first gate electrode portion is in a first direction from a first surface of the substrate toward a second surface of the substrate,
the second surface of the substrate is opposite to the first surface of the substrate,
the second gate electrode portion is in the first direction from the first surface of the substrate to the second surface of the substrate,
the second gate electrode portion is electrically connected to the first gate electrode portion,
the third gate electrode portion is in the first direction from the first surface towards the second surface of the substrate,
the third gate electrode portion is between the first gate electrode portion and the second gate electrode portion, and
the third gate electrode portion is electrically connected to each of the first gate electrode portion and the second gate electrode portion;
a first gate insulating film between an active region of the substrate and a first side surface of the first gate electrode portion, wherein
the active region of the substrate includes a channel of the transistor, and
the first side surface of the first gate electrode portion facing the active region of the substrate,
the first gate electrode portion faces the third gate electrode portion,
a first active region portion of the active region is between the first gate electrode portion and the third gate electrode portion,
the second gate electrode portion faces the third gate electrode portion, and
a second active region portion of the active region is between the second gate electrode portion and the third gate electrode portion;
a second gate insulating film between the second active region portion and the second gate electrode portion;
a third gate insulating film between the first active region portion and the third gate electrode portion;
a fourth gate insulating film between the second active region portion and the third gate electrode portion; and
a first insulating film on a second side surface of the first gate electrode portion, wherein
the second side surface of the first gate electrode portion is different from the first side surface of the first gate electrode portion,
the first insulating film is thicker than the first gate insulating film,
a depth of the first insulating film from the first surface of the substrate to the second surface of the substrate is one of same as a depth of the first gate electrode portion or deeper than the depth of the first gate electrode portion, and
in a cross section along the first direction, a width of an upper surface of the first gate electrode portion is wider than a width of a bottom surface of the first gate electrode portion.
2 . The solid-state imaging element according to claim 1 , wherein
the transistor further includes an upper gate electrode portion on an upper surface of the active region,
the upper gate electrode portion is between the first gate electrode portion and the second gate electrode portion,
the upper gate electrode portion connects the first gate electrode portion and the second gate electrode portion, and
the solid-state imaging element further comprises an upper gate insulating film between the upper surface of the active region and the upper gate electrode portion.
3 . The solid-state imaging element according to claim 2 , wherein
a second direction is perpendicular to a channel length direction of the transistor in a plane that is parallel to the first surface of the substrate, and
one of a width of a source of the transistor in the second direction or a width of a drain of the transistor in the second direction is equal to a width of the active region in the second direction.
4 . The solid-state imaging element according to claim 2 , wherein
a second direction is perpendicular to a channel length direction of the transistor in a plane that is parallel to the first surface of the substrate,
one of a width of a source of the transistor in the second direction or a width of a drain of the first transistor in the second direction is wider than a width of the active region in the second direction,
the solid-state imaging element further comprises a second insulating film that is between one of the source of the transistor or the drain of the transistor and the first gate electrode portion, and
the second insulating film is thicker than the first gate insulating film.
5 . The solid-state imaging element according to claim 3 , wherein the upper gate electrode portion is not above the source of the transistor and the drain of the transistor.
6 . The solid-state imaging element according to claim 1 , wherein
the transistor further includes a plurality of third gate electrode portions in the first direction from the first surface of the substrate towards the second surface of the substrate,
the plurality of third gate electrode portions includes the third gate electrode portion,
the plurality of third gate electrode portions is between the first gate electrode portion and the second gate electrode portion, and
the plurality of third gate electrode portions is electrically connected to each of the first gate electrode portion and the second gate electrode portion.
7 . The solid-state imaging element according to claim 1 , wherein the transistor further includes an upper gate electrode portion on each of an upper surface of the first active region portion and an upper surface of the second active region portion,
the upper gate electrode portion connects the first gate electrode portion to the third gate electrode portion,
the solid-state imaging element further comprises an upper gate insulating film between the upper surface of the first active region portion and the upper gate electrode portion, and
the upper gate insulating film is between the upper surface of the second active region portion and the upper gate electrode portion.
8 . The solid-state imaging element according to claim 7 , wherein
a second direction is perpendicular to a channel length direction of the transistor in a plane that is parallel to the first surface of the substrate, and
a width of the upper gate electrode portion in the second direction is wider than a sum of a width of the first active region portion in the second direction and a width of the second active region portion in the second direction.
9 . The solid-state imaging element according to claim 1 , wherein
a thickness of the first gate insulating film is equal to or more than 1 nm and less than 20 nm, and
a thickness of the first insulating film is equal to or more than 20 nm.
10 . The solid-state imaging element according to claim 1 , wherein in the cross section along the first direction, a width of an upper surface of the active region is narrower than a width of a bottom surface of the active region.
11 . The solid-state imaging element according to claim 1 , wherein a channel length of the first transistor is equal to or more than 200 nm.
12 . The solid-state imaging element according to claim 3 , wherein a width of the upper surface of the active region in the first direction is equal to or more than 20 nm and equal to or less than 200 nm.
13 . The solid-state imaging element according to claim 1 , wherein a depth from the first surface of the substrate to the bottom surface of the first gate electrode portion is equal to or more than 100 nm.
14 . The solid-state imaging element according to claim 1 , wherein the transistor is an amplification transistor that is configured to amplify a signal charge accumulated in a photodiode of each of the plurality of pixels.
15 . The solid-state imaging element according to claim 1 , wherein
the transistor is at least one of a transfer transistor, a reset transistor, or a selection transistor,
the transfer transistor is configured to transfer a signal charge accumulated in a photodiode of the plurality of pixels,
the reset transistor is configured to eliminate the signal charge of the photodiode, and
the selection transistor is configured to selectively connect the plurality of pixels to a vertical signal line.
16 . A method of manufacturing a solid-state imaging element, the method comprising:
forming a first trench in a first surface of a substrate;
forming a second trench in the first surface of the substrate;
forming a gate insulating film on each of an inner wall of the first trench and an inner wall of the second trench;
embedding an element isolation film in each of the first trench and the second trench;
forming a third trench by processing the element isolation film and exposing the gate insulating film in a channel region of the inner wall of the first trench;
forming a fourth trench by processing the element isolation film and exposing the gate insulating film in a channel region of the inner wall of the second trench;
embedding a first gate electrode in the third trench; and
embedding a second gate electrode in the fourth trench, wherein an upper gate electrode portion of the first gate electrode is connected to an upper gate electrode portion of the second gate electrode.