Method of manufacturing a semiconductor body and semiconductor device
In an embodiment a method for manufacturing a semiconductor body includes providing an subcarrier, generating a layer sequence with a first layer having a doped semiconductor material and a second layer deposited thereon, the second layer having an undoped semiconductor material, providing an electrochemical porosification of the first layer, wherein a degree of porosity is at least 20% by volume, forming mesa structures in the second layer and at least partially in the porous first layer and epitaxially producing a functional layer sequence having at least one planar third layer which is applied to the second layer comprising the mesa structures, wherein the at least one planar third layer has a specific lattice constant which is different from a lattice constant of the second layer.
1 . A semiconductor device comprising:
a subcarrier;
a layer sequence comprising a first layer having a doped semiconductor material and a second layer deposited thereon, the second layer comprising an undoped semiconductor material, wherein the first layer comprises at least one porous region, wherein a porosity level of the at least one porous region is at least 20% by volume;
a mesa structure introduced in the first and second layers and comprising several depressions; and
a functional layer sequence comprising at least one planar third layer deposited on the second layer and spanning the mesa structure, wherein the at least one planar third layer has a lattice constant which is different from a lattice constant of the second layer.
2 . The semiconductor device according to claim 1 , wherein a width of a depression is about ⅕ to 1/20 of a distance between two adjacent depressions.
3 . The semiconductor device according to claim 1 , wherein the first layer comprises at least one non-porous region at least partially surrounded by a porous region.
4 . The semiconductor device according to claim 3 , wherein the at least one non-porous region is separated from the porous region by a trench forming the mesa structure.
5 . The semiconductor device according to claim 1 , wherein the functional layer sequence comprises a multiple quantum well structure arranged on the at least one planar third layer.
6 . The semiconductor device according to claim 5 , wherein a first region of the multiple quantum well structure overlying a porous region of the first layer is configured to emit light of a first wavelength and a second region of the multiple quantum well structure overlying a non-porous region of the first layer is configured to emit light of a second shorter wavelength.
7 . The semiconductor device according to claim 1 , wherein the first layer comprises a first sub-region having a first degree of porosity and a second sub-region having a second degree of porosity, the first sub-region being separated from the second sub-region by an optional separation layer.
8 . The semiconductor device according to claim 1 , wherein the first layer comprises n-doping and the second layer is undoped, the first and second layers comprising the same base material.
9 . The semiconductor device according to claim 1 , wherein the second layer comprises an undoped GaN layer and the third layer comprises InGaN with an indium content in a range of 0.0001% to 25%.