Semiconductor layout pattern and manufacturing method thereof
The invention provides a semiconductor layout pattern, which comprises a first metal layer, wherein the first metal layer comprises a plurality of first patterns and a plurality of fishbone line patterns arranged on the same layer, wherein each fishbone line pattern comprises a principal axis pattern extending along a first direction and a plurality of branches arranged along a second direction, and each first pattern is located between two adjacent branches and the principal axis pattern, and a second metal layer is located on the first metal layer. A plurality of magnetic tunnel junction (MTJ) elements located on the second metal layer, wherein each magnetic tunnel junction element is arranged in a rhombic shape.
1 . A semiconductor layout pattern comprising:
a first metal layer comprising a plurality of first patterns and a plurality of fishbone line patterns, wherein each of the plurality of fishbone line patterns comprises a principal axis pattern extending along a first direction and a plurality of branches arranged along a second direction, and each of the plurality of first patterns is located between two adjacent branches of the plurality of branches and the principal axis pattern;
a second metal layer located on the first metal layer; and
a plurality of magnetic tunnel junction elements located on the second metal layer, wherein the magnetic tunnel junction elements are arranged in a rhombic shape.
2 . The semiconductor layout pattern according to claim 1 , wherein the plurality of branches are arranged on both sides of the principal axis pattern at equal intervals.
3 . The semiconductor layout pattern according to claim 2 , wherein any two adjacent branches of the plurality of branches and part of the principal axis pattern define an U-shaped opening, and each of the plurality of first patterns is located in a corresponding U-shaped opening.
4 . The semiconductor layout pattern according to claim 1 , wherein each of the plurality of first patterns comprises a rectangular pattern or an elliptical pattern.
5 . The semiconductor layout pattern according to claim 1 , wherein each of the plurality of first patterns is electrically connected to the second metal layer, and the second metal layer is electrically connected to one of the magnetic tunneling junction elements.
6 . The semiconductor layout pattern according to claim 1 , wherein each of the plurality of fishbone line patterns is electrically connected to a selection line.
7 . The semiconductor layout pattern according to claim 1 , wherein the plurality of magnetic tunnel junction elements are arranged in the rhombic shape, wherein:
any four adjacent magnetic tunneling junction elements of the plurality of magnetic tunnel junction elements can be arranged in the rhombic shape, wherein no other magnetic tunneling junction elements are included between the four adjacent magnetic tunneling junction elements;
two of the four adjacent magnetic tunneling junction elements are aligned in the first direction, and the other two of the four adjacent magnetic tunneling junction elements are aligned in the second direction.
8 . The semiconductor layout pattern according to claim 1 , wherein the first direction and the second direction are perpendicular to each other.
9 . The semiconductor layout pattern according to claim 1 , wherein the second metal layer comprises a plurality of second patterns, and each magnetic tunneling junction element is located on one of the second patterns.
10 . The semiconductor layout pattern according to claim 1 , further comprising a transistor disposed under the first metal layer, wherein the transistor comprises a gate, a source and a drain, and wherein one of the plurality of fishbone line patterns is electrically connected to the source of the transistor, and one of the plurality of first patterns is electrically connected to the drain of the transistor.
11 . A method for forming a semiconductor layout pattern, comprising:
forming a first metal layer comprising a plurality of first patterns and a plurality of fishbone line patterns, wherein each of the plurality of fishbone line patterns comprises a principal axis pattern extending along a first direction and a plurality of branches arranged along a second direction, and each of the plurality of first patterns is located between two adjacent branches of the plurality of branches and the principal axis pattern;
forming a second metal layer on the first metal layer; and
forming a plurality of magnetic tunnel junction elements on the second metal layer, wherein the magnetic tunnel junction elements are arranged in a rhombic shape.
12 . The method for forming a semiconductor layout pattern according to claim 11 , wherein the plurality of branches are arranged on both sides of the principal axis pattern at equal intervals.
13 . The method for forming a semiconductor layout pattern according to claim 12 , wherein any two adjacent branches of the plurality of branches and part of the principal axis pattern define an U-shaped opening, and each of the plurality of first patterns is located in a corresponding U-shaped opening.
14 . The method for forming a semiconductor layout pattern according to claim 11 , wherein each of the plurality of first patterns comprises a rectangular pattern or an elliptical pattern.
15 . The method for forming a semiconductor layout pattern according to claim 11 , wherein each of the plurality of first patterns is electrically connected to the second metal layer, and the second metal layer is electrically connected to one of the magnetic tunneling junction elements.
16 . The method for forming a semiconductor layout pattern according to claim 11 , wherein each of the plurality of fishbone line patterns is electrically connected to a selection line.
17 . The method for forming a semiconductor layout pattern according to claim 11 , wherein the plurality of magnetic tunnel junction elements are arranged in the rhombic shape, wherein:
any four adjacent magnetic tunneling junction elements of the plurality of magnetic tunnel junction elements can be arranged in the rhombic shape, wherein no other magnetic tunneling junction elements are included between the four adjacent magnetic tunneling junction elements;
two of the four adjacent magnetic tunneling junction elements are aligned in the first direction, and the other two of the four adjacent magnetic tunneling junction elements are aligned in the second direction.
18 . The method for forming a semiconductor layout pattern according to claim 11 , wherein the first direction and the second direction are perpendicular to each other.
19 . The method for forming a semiconductor layout pattern according to claim 11 , wherein the second metal layer comprises a plurality of second patterns, and each magnetic tunneling junction element is located on one of the second patterns.
20 . The method for forming a semiconductor layout pattern according to claim 11 , further comprising a transistor disposed under the first metal layer, wherein the transistor comprises a gate, a source and a drain, and wherein one of the plurality of fishbone line patterns is electrically connected to the source of the transistor, and one of the plurality of first patterns is electrically connected to the drain of the transistor.