Method of forming expandable doped oxide films for advanced semiconductor applications
Films that can be useful in large area gap fill applications, such as in the formation of advanced 3D NAND devices, involve processing a semiconductor substrate by depositing on a patterned semiconductor substrate a doped silicon oxide film a doped silicon oxide film configured to expand upon annealing at a temperature above the films glass transition temperature, and annealing the doped silicon oxide film to a temperature above the film glass transition temperature. In some embodiments, reflow of the film may occur. The composition and processing conditions of the doped silicon oxide film may be tailored so that the film exhibits substantially zero as-deposited stress and substantially zero stress shift post-anneal.
1 . A method of processing a semiconductor substrate, the method comprising:
providing a patterned semiconductor substrate;
depositing on the patterned semiconductor substrate a doped silicon oxide film configured to expand upon annealing at a temperature above a glass transition temperature of the doped silicon oxide film, wherein the doped silicon oxide film has a dopant concentration of greater than 6 wt. % B and 0 to 3 wt. % P; and
annealing the doped silicon oxide film to a temperature above the glass transition temperature of the doped silicon oxide film, whereby the doped silicon oxide film expands upon annealing.
2 . The method of claim 1 , wherein the dopant concentration of the doped silicon oxide film comprises 7-10 wt. % B.
3 . The method of claim 1 , wherein the dopant concentration of the doped silicon oxide film comprises less than 7 wt. % B and 0 wt. % P.
4 . The method of claim 1 , wherein the dopant concentration of the doped silicon oxide film comprises at least 7 wt. % B and greater than 0 wt. % P.
5 . The method of claim 1 , wherein the dopant concentration of the doped silicon oxide film comprises about 7 wt. % B and about 1.5 wt. % P.
6 . The method of claim 1 , wherein the doped silicon oxide film is deposited by a chemical vapor deposition (CVD) based process using precursors for silicon oxide, a B dopant, and a P dopant.
7 . The method of claim 6 , wherein the CVD is a plasma enhanced CVD (PECVD) process flowing the precursors for the silicon oxide, the B dopant, and the P dopant, wherein the precursor for the silicon oxide is tetraethyl orthosilicate (TEOS), wherein the precursor for the B dopant is triethylborate (TEB), wherein the precursor for the P dopant is triethylphosphate (TEPO), and wherein the precursors for the silicon oxide, the B dopant, and the P dopant are present in a ratio from 50:20:0 to 50:25:1.
8 . The method of claim 1 , further comprising depositing an undoped silicon oxide capping layer on the doped silicon oxide film.
9 . The method of claim 1 , wherein the patterned semiconductor substrate is a 3D NAND structure having alternating oxide and nitride or polysilicon layers in a staircase pattern, and wherein the doped silicon oxide film is deposited over the staircase pattern.
10 . The method of claim 1 , wherein a deposition rate of the doped silicon oxide film is greater than 1 μm/min.
11 . The method of claim 1 , wherein an as-deposited stress and a stress shift of the doped silicon oxide film are about zero.
12 . The method of claim 1 , wherein the doped silicon oxide film is deposited at a thickness up to 20 μm by a single-pass deposition.
13 . The method of claim 1 , wherein the annealing of the doped silicon oxide film causes reflow of the doped silicon oxide film to occur.
14 . A semiconductor device, comprising:
a 3D NAND structure having alternating oxide and nitride or polysilicon layers in a staircase pattern; and
a doped silicon oxide film disposed and annealed on the staircase pattern;
wherein the doped silicon oxide film has a dopant concentration in a range of greater than at least 6 wt. % B and 0 to 3 wt. % P.
15 . The device of claim 14 , wherein the doped silicon oxide film comprises 7-10 wt. % B and 0-3 wt. % P dopants.
16 . The device of claim 14 , wherein the doped silicon oxide film comprises less than 7 wt. % B and 0 wt. % P dopants.
17 . The device of claim 14 , wherein the doped silicon oxide film comprises at least 7 wt. % B and greater than 0 wt. % P dopants.
18 . The device of claim 14 , wherein the doped silicon oxide film comprises about 7 wt. % B and about 1.5 wt. % P dopants.
19 . The device of claim 14 , further comprising depositing an undoped silicon oxide capping layer on the doped silicon oxide film.
20 . An apparatus for processing substrates, the apparatus comprising:
a process chamber having a chuck;
a gas source connected with the process chambers and associated flow-control hardware; and
substrate handling hardware;
a controller having a processor and a memory, wherein
the processor and the memory are communicatively connected with one another,
the processor is at least operatively connected with the flow-control and substrate handling hardware, and
the memory stores computer-executable instructions for controlling the processor to at least control the flow-control hardware and substrate handling hardware by:
providing a patterned semiconductor substrate;
depositing on a patterned semiconductor substrate disposed in the chamber a doped silicon oxide film configured to expand upon annealing to a temperature above a glass transition temperature of the doped silicon oxide film, wherein the doped silicon oxide film has a dopant concentration of greater than 6 wt. % B and 0 to 3 wt. % P; and
annealing the doped silicon oxide film to a temperature above the glass transition temperature of the doped silicon oxide film.