Computing device and electronic device guaranteeing bandwidth per computational performance
A computing device includes: a processor; a memory stack in which memories connected to the processor are stacked; and a substrate disposed under the processor, wherein a memory bandwidth between the processor and the memory stack is five or less times a network bandwidth between the processor and the substrate.
1 . A device comprising:
a processor connected to a memory stack in which memories connected to the processor are stacked,
wherein the processor is connected to the memory stack through a through-silicon via (TSV), and
wherein a memory bandwidth established through the TSV between the processor and the memory stack is five or less times a network bandwidth between the processor and a substrate disposed under the processor.
2 . The device of claim 1 , wherein
a computational performance of the processor is determined based on an area of the processor, and
the network bandwidth per the computational performance of the processor is greater than or equal to 0.1 bytes per flop.
3 . The device of claim 1 , wherein an area of the processor is less than five times an area of the substrate.
4 . The device of claim 1 , wherein
the memory bandwidth is determined based on a TSV area present between the processor and the memory stack, and
the network bandwidth is determined based on an input/output (I/O) area of the processor and an area of the substrate.
5 . The device of claim 1 , wherein the processor is configured to:
determine the memory bandwidth by controlling a number of TSV connections to the memory stack and a memory signal frequency of the memory stack; and
determine the network bandwidth by controlling a number of input/output (I/O) connections to the substrate and an I/O signal frequency of the substrate.
6 . The device of claim 1 , wherein the processor is disposed on the memory stack to be directly connected to the memory stack without a buffer.
7 . The device of claim 6 , wherein
the processor is disposed in a direction in which a circuit board of the processor faces the substate,
the processor and the substrate are connected through a bump.
8 . The device of claim 6 , wherein
the processor is disposed in a direction in which a circuit board of the processor faces the memory stack,
the processor and the memory stack are connected as the TSV connected to the memory stack and an upper end pad of the processor are connected through a micro-bump, and
the processor and the substrate are connected through a bump.
9 . The device of claim 1 , further comprising:
a buffer configured to connect the processor and the memory stack; and
an interposer disposed between the processor and the substrate,
wherein the memory stack is disposed on the buffer, and is connected to the processor through the buffer and the interposer.
10 . The device of claim 1 , wherein
a number of channels used in the device is determined based on a total number of available lanes and a number of allocated lanes per channel of the device,
the total number of available lanes is determined by either one or both an area of the processor and an area of the substrate, and
the number of allocated lanes per channel is determined according to a network protocol of the device.
11 . The device of claim 1 , further comprising the memory stack and the substrate.
12 . A device comprising:
a memory stack in which memories connected to a processor are stacked,
wherein the memory stack is connected to the processor through a through-silicon via TSV), and
wherein a memory bandwidth established through the TSV between the memory stack and the processor is five or less times a network bandwidth between the processor and a substrate disposed under the processor.
13 . The device of claim 12 , wherein
a computational performance of the processor is determined based on an area of the processor, and
the network bandwidth per the computational performance of the processor is greater than or equal to 0.1 bytes per flop.
14 . The device of claim 12 , wherein an area of the substrate is five or greater times an area of the processor.
15 . The device of claim 12 , wherein
the memory bandwidth is determined based on a TSV area present between the processor and the memory stack, and
the network bandwidth is determined based on an input/output (I/O) area of the processor and an area of the substrate.
16 . The device of claim 12 , wherein
the memory bandwidth is determined by controlling a number of TSV connections to the memory stack and a memory signal frequency of the memory stack, and
the network bandwidth is determined by controlling a number of input/output (I/O) connections to the substrate and an I/O signal frequency of the substrate.
17 . The device of claim 12 , wherein the memory stack is disposed on the processor to be directly connected to the processor without a buffer.
18 . The device of claim 17 , wherein
the memory stack is disposed in a direction in which the memory stack faces a circuit board of the processor,
the memory stack and the processor are connected as the TSV connected to the memory stack and the memory stack and an upper end pad of the processor are connected through a micro-bump.
19 . The device of claim 12 , further comprising:
a buffer configured to connect the memory stack and the processor; and
an interposer disposed between the processor and the substrate,
wherein the memory stack is disposed on the buffer, and is connected to the processor through the buffer and the interposer.
20 . The device of claim 12 , wherein
a number of channels used in the device is determined based on a total number of available lanes and a number of allocated lanes per channel of the device,
the total number of available lanes is determined by either one or both an area of the processor and an area of the substrate, and
the number of allocated lanes per channel is determined according to a network protocol of the device.