IP Library Granted Patent US 12713891
Granted Patent B2
US 12713891 · App. 18/369,109 · Granted Aug 18, 2026

Electronic device

Inventors: Chiung-Ying Kuo (Kaohsiung, TW); Jung Jui Kang (Kaohsiung, TW); Hung-Chun Kuo (Kaohsiung, TW); Chun-Yen Ting (Kaohsiung, TW)
Assignee: Advanced Semiconductor Engineering, Inc.
H10W20/20H05K1/0231H10W42/20
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Quick Facts
Patent No.
US 12713891
App. No.
18/369,109
Granted
Aug 18, 2026
Kind
B2
Abstract

An electronic device is disclosed. The electronic component has a front side and a backside opposite to the front side. The front side is configured to receive a first power. The backside is configured to receive a second power greater than the first power.

Claims (26)

1 . An electronic device, comprising:

an electronic component having a front side and a backside opposite to the front side, wherein the front side is configured to receive a first power, and the backside is configured to receive a second power greater than the first power;

a first circuit disposed adjacent to the front side, wherein the first circuit comprises a first region configured to receive the first power and a second region configured to transceive a first non-power signal,

wherein the first circuit comprises a third region configured to transceive a second non-power signal, wherein a data rate of the second non-power signal is different from a data rate of the first non-power signal,

and wherein the second region is disposed between the first region and the third region and the data rate of the first non-power signal is less than the data rate of the second non-power signal.

2 . The electronic device of claim 1 , wherein the first region is located at a central region of the first circuit, and the second region is located at a peripheral region of the first circuit.

3 . The electronic device of claim 1 , wherein the first circuit comprises a fourth region configured to block an electromagnetic interference between the first region, the second region, and the third region.

4 . The electronic device of claim 1 , further comprising:

a second circuit adjacent to the backside, wherein a density of the second circuit is less than a density of the first circuit.

5 . The electronic device of claim 4 , wherein a line width/line space (L/S) of the second circuit is greater than that of the first circuit.

6 . The electronic device of claim 4 , wherein a thickness of a trace of the second circuit is greater than that of a trace of the first circuit.

7 . An electronic device, comprising:

an electronic component having a front side and a backside opposite to the front side, wherein the front side is configured to receive a first power, and the backside is configured to receive a second power greater than the first power;

a first circuit disposed adjacent to the front side, wherein the first circuit comprises a first region configured to receive the first power and a second region configured to transceive a first non-power signal; and

a second circuit adjacent to the backside, wherein the second circuit comprises a first region configured to receive the second power and a second region configured to receive a third power different from the second power.

8 . An electronic device, comprising:

an electronic component having a front side and a backside;

a first circuit under the front side and configured to provide a first functional region of the electronic component with a first power; and

a second circuit over the backside and configured to provide a second functional region of the electronic component with a second power,

wherein a density of the first circuit is less than that of the second circuit,

wherein the first circuit is further configured to transceive a non-power signal,

and wherein the first circuit comprises a high speed data region and a low speed data region, and the high speed data region is closer to an edge of the first circuit than the low speed data region is.

9 . The electronic device of claim 8 , wherein the first circuit comprises a power transmission region disposed between the low speed data region and the high speed data region.

10 . The electronic device of claim 8 , wherein the second circuit is further configured to provide the first functional region of the electronic component with a third power less than the second power.

11 . The electronic device of claim 10 , wherein the second circuit comprises a first impedance matching trace configured to transmit the second power and a second impedance matching trace configured to transmit the third power, and a dimension of the first impedance matching trace is greater than a dimension of the second impedance matching trace in a cross-sectional view.

12 . The electronic device of claim 8 , wherein the second circuit vertically overlaps the first functional region and the second functional region.