Three-dimensional semiconductor memory device and electronic system including the same

1 . A three-dimensional semiconductor memory device, comprising:

a first substrate that includes a cell array region and a contact region that extends from the cell array region;

a stack structure that includes interlayer dielectric layers and gate electrodes that are alternately stacked on the first substrate;

a second dielectric layer on the stack structure;

a cell contact plug that extends through the second dielectric layer and the contact region of the stack structure;

a selection mold structure on the stack structure and the second dielectric layer;

a third dielectric layer on the selection mold structure; and

a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug,

wherein the dummy through contact has a second width in a direction that is parallel to a top surface of the first substrate,

wherein the capping through contact has a first width in the direction that is parallel to the top surface of the first substrate,

wherein the second width is different from the first width, and

wherein the selection mold structure includes a selection semiconductor layer.

2 . The three-dimensional semiconductor memory device of claim 1 , further comprising a contact plug that extends through the third dielectric layer,

wherein the contact plug has a third width in the direction that is parallel to the top surface of the first substrate, and

wherein the second width is different from the third width.

3 . The three-dimensional semiconductor memory device of claim 2 , wherein the second width is greater than the first width, and

wherein the third width is greater than the first width.

4 . The three-dimensional semiconductor memory device of claim 2 , wherein the third width is greater than the first width, and

wherein the first width is greater than the second width.

5 . The three-dimensional semiconductor memory device of claim 1 , wherein

the selection semiconductor layer includes polycrystalline silicon.

6 . The three-dimensional semiconductor memory device of claim 5 , wherein a top surface of the dummy through contact is coplanar with a top surface of the selection semiconductor layer.

7 . The three-dimensional semiconductor memory device of claim 1 , wherein the selection mold structure includes:

a first capping dielectric layer;

a second capping dielectric layer;

a third capping dielectric layer;

the selection semiconductor layer; and

a mold dielectric layer,

wherein the first capping dielectric layer and the third capping dielectric layer include silicon oxide, and the second capping dielectric layer includes a silicon nitride layer.

8 . The three-dimensional semiconductor memory device of claim 1 , wherein the cell contact plug, the dummy through contact, and the capping through contact include tungsten (W).

9 . The three-dimensional semiconductor memory device of claim 1 , further comprising:

a peripheral circuit structure that includes peripheral circuit transistors on the first substrate;

a second substrate on the peripheral circuit structure;

a source structure between the stack structure and the second substrate; and

a vertical channel structure in a vertical channel hole that extends through the stack structure and the source structure,

wherein the vertical channel structure includes a data storage pattern and a vertical semiconductor pattern that are on an inner sidewall of the vertical channel hole, and

wherein the source structure contacts a sidewall of the vertical semiconductor pattern of the vertical channel structure.

10 . The three-dimensional semiconductor memory device of claim 9 , further comprising an upper vertical channel structure that extends through the selection mold structure,

wherein a lower portion of the upper vertical channel structure is connected to an upper portion of the vertical channel structure.

11 . The three-dimensional semiconductor memory device of claim 9 , further comprising a mold structure between the stack structure and the second substrate,

wherein the mold structure includes a first buffer dielectric layer, a first semiconductor layer on the first buffer dielectric layer, a second buffer dielectric layer on the first semiconductor layer, and a second semiconductor layer on the second buffer dielectric layer.

12 . The three-dimensional semiconductor memory device of claim 9 , further comprising a plurality of cell contact plugs and a mold structure between the second substrate and the stack structure,

wherein the plurality of cell contact plugs extend through the stack structure, the mold structure, and the second substrate and are connected to the peripheral circuit transistors, and

wherein each of the plurality of cell contact plugs is in contact with one of the gate electrodes and is spaced apart from others of the gate electrodes across a first dielectric pattern and in a direction that is parallel to a top surface of the second substrate.

13 . The three-dimensional semiconductor memory device of claim 12 , wherein

each of the plurality of cell contact plugs is spaced apart in the direction parallel to the top surface of the second substrate from the second substrate across a second dielectric pattern, and

the first dielectric pattern, the second dielectric pattern, and the interlayer dielectric layers of the stack structure include a same material.

14 . A three-dimensional semiconductor memory device, comprising:

a first substrate that includes a cell array region and a contact region that extends from the cell array region;

a stack structure that includes interlayer dielectric layers and gate electrodes that are alternately stacked on the first substrate;

a second dielectric layer on the stack structure;

a cell contact plug that extends through the second dielectric layer and the contact region of the stack structure;

a selection mold structure on the stack structure and the second dielectric layer;

a third dielectric layer on the selection mold structure;

a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug; and

a spacer dielectric layer between the selection mold structure and a sidewall of the capping through contact,

wherein the selection mold structure includes a selection semiconductor layer.

15 . The three-dimensional semiconductor memory device of claim 14 , wherein the spacer dielectric layer includes silicon oxide.

16 . The three-dimensional semiconductor memory device of claim 14 , wherein

an upper portion of the spacer dielectric layer contacts a lower portion of the dummy through contact, and

a lower portion of the spacer dielectric layer contacts an upper portion of the cell contact plug.

17 . The three-dimensional semiconductor memory device of claim 14 , wherein

a top surface of the spacer dielectric layer is coplanar with a bottom surface of the selection semiconductor layer.

18 . An electronic system, comprising:

a first substrate that includes a cell array region and a contact region that extends from the cell array region;

a three-dimensional semiconductor memory device that includes a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure, a dielectric layer on the cell array structure, and an input/output pad on the dielectric layer and connected to the peripheral circuit structure; and

a controller connected to the three-dimensional semiconductor memory device through the input/output pad,

wherein the cell array structure includes:

a second substrate on the peripheral circuit structure;

a stack structure that includes interlayer dielectric layers and gate electrodes that are alternately stacked on the second substrate;

a second dielectric layer on the stack structure;

a cell contact plug that extends through the second dielectric layer and the contact region of the stack structure;

a selection mold structure on the stack structure and the second dielectric layer;

a third dielectric layer on the selection mold structure; and

a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug,

wherein the dummy through contact has a second width in a direction that is parallel to a top surface of the first substrate,

wherein the capping through contact has a first width in the direction that is parallel to the top surface of the first substrate,

wherein the second width is greater than the first width, and

wherein the selection mold structure includes a selection semiconductor layer.

19 . The electronic system of claim 18 , further comprising a spacer dielectric layer between the selection mold structure and a sidewall of the capping through contact.

20 . The electronic system of claim 18 , wherein the peripheral circuit structure includes:

peripheral circuit transistors on the first substrate; and

first bonding pads connected to the peripheral circuit transistors, wherein the cell array structure further includes:

conductive lines connected to cell contact plugs;

vertical channel structures that extend through the stack structure on the cell array region;

bit lines connected to the vertical channel structures; and

second bonding pads connected to the conductive lines and the bit lines,

wherein the first bonding pads and the second bonding pads are integrally connected into a single unitary body.