Interconnect structure and methods of forming the same
An interconnect structure, along with methods of forming such, are described. The structure includes a dielectric layer, a conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer, wherein the conductive layer includes a first portion and a second portion adjacent the first portion. The structure also includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a dielectric material disposed between and in contact with the first and second barrier layers, wherein a bottom surface of the second barrier layer and a bottom surface of the dielectric material are substantially co-planar.
1 . A method for forming an interconnect structure, comprising:
forming a conductive layer over a dielectric layer;
forming one or more openings in the conductive layer to expose portions of the dielectric layer, wherein the one or more openings separates the conductive layer into one or more portions;
forming a blocking layer on an exposed surface of the dielectric layer;
forming barrier layers in contact with the portions of the conductive layer;
forming a capping layer on the barrier layers;
forming a dielectric material on the capping layer to fill the one or more openings; and
performing a planarization process until the portions of the conductive layer are exposed.
2 . The method of claim 1 , further comprising:
prior to forming the capping layer, removing the blocking layer.
3 . The method of claim 1 , wherein the blocking layer comprises a self-assembled monolayer (SAM).
4 . The method of claim 1 , wherein the barrier layers comprise a refractory metal nitride.
5 . The method of claim 1 , wherein the barrier layers are formed by atomic layer deposition.
6 . The method of claim 1 , further comprising:
after the planarization process, selectively forming a cap layer on a top surface of the portions of the conductive layer.
7 . The method of claim 1 , further comprising:
forming a metal oxide layer on the dielectric material after the planarization process.
8 . The method of claim 1 , wherein top surfaces of the conductive layer and the dielectric material are substantially co-planar after the planarization process.
9 . A method for forming an interconnect structure, comprising:
forming a conductive layer over a dielectric layer;
forming one or more openings in the conductive layer;
forming a blocking layer on exposed portions of the dielectric layer;
selectively forming barrier layers on the conductive layer;
removing the blocking layer;
forming a dielectric material directly on the dielectric layer and between adjacent portions of the conductive layer; and
performing a planarization process until the conductive layer is exposed.
10 . The method of claim 9 , wherein removing the blocking layer comprises a plasma treatment.
11 . The method of claim 9 , wherein the dielectric material forms an inverted T-shaped profile at a bottom portion.
12 . The method of claim 11 , wherein the dielectric material contacts a bottom surface of the barrier layers.
13 . The method of claim 9 , wherein the barrier layers comprise titanium nitride or tantalum nitride.
14 . The method of claim 9 , further comprising:
prior to forming the barrier layers, forming a glue layer on sidewalls of the portions of the conductive layer.
15 . A method for forming an interconnect structure, comprising:
forming a conductive layer over a dielectric layer;
forming one or more openings in the conductive layer to expose portions of the dielectric layer, wherein the one or more openings separates the conductive layer into one or more portions;
forming a blocking layer on an exposed surface of the dielectric layer;
forming barrier layers on the portions of the conductive layer;
removing the blocking layer;
forming a capping layer on the barrier layers and the dielectric layer;
forming a sacrificial layer in the one or more openings and over a hard mask;
recessing the sacrificial layer to a level below a top surface of the portions of the conductive layer;
forming a support layer on the capping layer and the recessed sacrificial layer;
forming a dielectric material on the support layer to fill remaining portions of the one or more openings;
removing the sacrificial layer to form an air gap between neighboring portions of the conductive layer; and
performing a planarization process until the portions of the conductive layer are exposed.
16 . The method of claim 15 , wherein removing the sacrificial layer comprises performing a UV curing process.
17 . The method of claim 15 , wherein the support layer is porous and comprises a silicon-containing material selected from the group consisting of SiO, SiCO, SiNO, SiCN, and SiCON.
18 . The method of claim 15 , further comprising:
after the planarization process, forming a metal oxide layer on a top surface of the dielectric material.
19 . The method of claim 15 , wherein the air gap has an inverted T-shaped profile.
20 . The method of claim 15 , further comprising:
selectively forming a cap layer on a top surface of the portions of the conductive layer after the planarization process.