Semiconductor structure having back-side contact and manufacturing method thereof

1 . A method, comprising:

forming a plurality of semiconductor sheets on a front-side of a semiconductive layer that is on a front-side of a substrate, the plurality of semiconductor sheets being stacked along a first direction;

forming a gate strip surrounding each of the semiconductor sheets;

forming a dielectric gate offset from the gate strip, the dielectric gate extending from above the gate strip to below the gate strip;

forming a plurality of dielectric layers on the semiconductive layer and at opposite sides of the gate strip, at least one dielectric layer of the plurality of dielectric layers being positioned between the dielectric gate and the plurality of semiconductor sheets, a bottommost surface of the at least one dielectric layer being above a bottommost surface of the dielectric gate in the first direction;

forming a plurality of source/drain structures on the dielectric layers and on either side of each of the semiconductor sheets;

performing a planarization process on a back-side of the substrate to expose the semiconductive layer;

etching the semiconductive layer from a back-side of the semiconductive layer to form a first opening exposing a first one of the dielectric layers, while a second one of the dielectric layers remains covered by the semiconductive layer;

selectively removing the first one of the dielectric layers through the first opening to form a second opening exposing one of the source/drain structures;

forming a contact having a back-side portion in the first opening and a front-side portion in the second opening; and

forming a power supply voltage line on a back-side of the contact, the power supply voltage line having an uppermost surface contiguous with a bottommost surface of the dielectric gate.

2 . The method of claim 1 , wherein when viewed in a cross section taken along a lengthwise direction of one of the semiconductor sheets, the contact is a stepped sidewall structure having a first sidewall connecting the power supply voltage line, a second sidewall connecting the first one of the source/drain structures and laterally set back from the first sidewall, and a horizontal surface connecting the first sidewall to the second sidewall.

3 . The method of claim 2 , wherein the horizontal surface has a length greater than about 2 nm when viewed in the cross section.

4 . The method of claim 1 , wherein when viewed in a cross section taken along a direction in parallel with a lengthwise direction the gate strip, the back-side portion of the contact has a same dimension as the front-side portion of the contact.

5 . The method of claim 1 , wherein when viewed in a cross section taken along a lengthwise direction of one of the semiconductor sheets, the back-side portion of the contact has a greater lateral dimension than the remained second one of the dielectric layers.

6 . The method of claim 1 , further comprising:

before forming the contact, forming a silicide layer on a back-side of the one of the source/drain structures.

7 . The method of claim 6 , wherein the silicide layer is further conformally formed on sidewalls of the first and second openings.

8 . The method of claim 1 , further comprising:

before forming the contact, conformally forming a dielectric layer on sidewalls of the first and second openings.

9 . The method of claim 1 , further comprising:

forming a back-side dielectric layer between the semiconductive layer and the power supply voltage line, wherein the contact penetrates through the back-side dielectric layer.

10 . The method of claim 1 , further comprising:

performing an implantation process on the semiconductive layer with a dopant, wherein the dopant has a same conductivity type as the source/drain structures.

11 . A method, comprising:

forming a plurality of nanostructures arranged in a first direction on a semiconductor strip upwardly extending from a front-side of a substrate;

forming a dielectric gate offset from the plurality of nanostructures, the dielectric gate extending from above the plurality of nanostructures in the first direction to below an uppermost surface of the semiconductor strip in the first direction;

forming a plurality of leakage barriers on the semiconductor strip;

growing a plurality of epitaxial patterns on opposite sides of the nanostructures and on the leakage barriers;

forming a gate pattern across the nanostructures and between the epitaxial patterns;

performing a planarization process on a back-side of the substrate to expose the semiconductor strip;

etching the semiconductor strip to expose one of the leakage barriers;

removing the one of the leakage barriers to expose one of the epitaxial patterns;

after removing the one of the leakage barriers, forming a power conductive contact extending through the semiconductor strip and on the one of the epitaxial patterns, the power conductive contact being a stepped sidewall structure, and a back-side of the power conductive contact having a greater lateral dimension than a front-side of the power conductive contact; and

forming a power supply voltage line on the back-side of the power conductive contact, the power supply voltage line having an uppermost surface contiguous with a bottommost surface of the dielectric gate.

12 . The method of claim 11 , further comprising:

forming a spacer on a sidewall of the gate pattern, wherein the power conductive contact overlaps the spacer from a top view.

13 . The method of claim 11 , wherein the back-side of the power conductive contact has opposite two sidewalls, the sidewalls having a distance therebetween in a range from about 13 nm to about 50 nm.

14 . The method of claim 11 , wherein the front-side of the power conductive contact has opposite two sidewalls, the sidewalls having a distance therebetween in a range from about 9 nm to about 20 nm.

15 . The method of claim 11 , further comprising:

forming a shallow trench isolation (STI) structure laterally surrounding the semiconductor strip, the STI structure being used as an etch stop layer during the planarization process.

16 . The method of claim 11 , wherein forming the dielectric gate comprises:

forming a dummy gate pattern on the front-side of the substrate and extending in parallel with a lengthwise direction of the gate pattern from a top view, the dummy gate pattern having a back-side interrupting the semiconductor strip.

17 . A semiconductor structure, comprising:

a transistor on a front side of a silicon layer, the transistor comprising a channel region, a gate structure surrounding the channel region, and a plurality of source/drain regions on opposite sides of the gate structure;

a dielectric gate between the transistor and a second transistor adjacent the transistor, the dielectric gate extending from above the gate structure to below the gate structure;

a contact extending through the silicon layer and on a back-side of one of the source/drain regions, wherein from a cross-sectional view, the contact has a back-side sidewall, a front-side sidewall connecting the back-side of the one of the source/drain regions and laterally set back from the back-side sidewall, and a horizontal surface connecting the back-side sidewall to the front-side sidewall;

a front-side power supply voltage line electrically connected to a front-side of the one of the source/drain regions; and

a back-side power supply voltage line electrically connected to the contact, the back-side power supply voltage line having an upper surface contiguous with a bottommost surface of the contact and contiguous with a bottommost surface of the dielectric gate.

18 . The semiconductor structure of claim 17 , further comprising:

a silicide layer lining the back-side sidewall and the front-side sidewall of the contact.

19 . The semiconductor structure of claim 17 , further comprising:

a back-side dielectric layer between the silicon layer and the back-side power supply voltage line, wherein the contact penetrates through the back-side dielectric layer.

20 . The semiconductor structure of claim 17 , wherein:

the dielectric gate extends in parallel with a lengthwise direction of the gate structure, and has a back-side inlaid in the silicon layer from a cross sectional view.