Semiconductor device assemblies with coplanar interconnect structures, and methods for making the same
A semiconductor device assembly is provided. The assembly includes a substrate with an inner and outer surface, a plurality of semiconductor devices disposed on the inner surface, a central interconnect structure disposed between the devices, a plurality of peripheral interconnect structures disposed around the devices, and an encapsulant material at least partially encapsulating the devices and the interconnects. The central interconnect structure includes a plurality of conductors and a sheath of dielectric material that surrounds and electrically isolates each of the plurality of conductors. Each of the peripheral interconnect structures is electrically coupled to at least one of the semiconductor devices. The encapsulant comprises a different material than the dielectric material.
1 . A semiconductor device assembly, comprising:
a substrate, including:
an inner surface and an outer surface;
a plurality of vertical stacks of semiconductor devices disposed on the inner surface and extending above the inner surface by a first distance, each vertical stack of semiconductor devices comprising one or more memory dies;
a central interconnect structure disposed between the plurality of vertical stacks of semiconductor devices on the inner surface and extending above the inner surface by a second distance greater than the first distance, including:
a plurality of conductors and a sheath of dielectric material that surrounds and electrically isolates each of the plurality of conductors, each of the plurality of conductors electrically coupled to a corresponding one of the plurality of semiconductor devices;
a plurality of peripheral interconnect structures disposed around the vertical stacks of semiconductor devices on the inner surface, each of the peripheral interconnect structures in the plurality electrically coupled to at least one of the semiconductor devices, each of the plurality of peripheral interconnect structures extending above the inner surface by the second distance; and
an encapsulant material at least partially encapsulating the devices and the interconnects, wherein the encapsulant comprises a different material than the dielectric material,
wherein the central and peripheral interconnect structures electrically couple the plurality of semiconductor devices to each other, or to an electrically conductive structure disposed at the inner surface of the substrate, or to both.
2 . The semiconductor device assembly of claim 1 , wherein the peripheral interconnect structures include a conductor surrounded by a sheath of dielectric material.
3 . The semiconductor device assembly of claim 1 , wherein the outer surface of the substrate is exclusive of any external conductive surfaces.
4 . The semiconductor device assembly of claim 1 , wherein the central interconnect structure or the plurality of peripheral interconnect structures extend to a top surface of the encapsulant material, or both extend to a top surface of the encapsulant material.
5 . The semiconductor device assembly of claim 1 , wherein each of the plurality of conductors of the central interconnect is coupled to the corresponding one of the plurality of semiconductor devices by either (i) a wire bond extending from a top surface of the conductor to a top surface of the corresponding semiconductor device, or (ii) conductive structures in the substrate extending from a bottom surface of the conductor to a bottom surface of the corresponding semiconductor device.
6 . The semiconductor device assembly of claim 1 , wherein each of the peripheral and central interconnect structures further includes a contact pad electrically coupled to an electrically conductive structure disposed at the inner surface of the substrate.
7 . The semiconductor device assembly of claim 1 , wherein each of the peripheral and central interconnect structures further comprise:
a solder joint electrically coupled to an electrically conductive structure disposed at the inner surface of the substrate.
8 . The semiconductor device assembly of claim 1 , wherein each of the peripheral interconnect structures have a first height, the central interconnect structure has a second height, and each of the plurality of semiconductor devices has a third height, and wherein either (i) the first height is greater than the second and third heights, or (ii) the second height is greater than the first and third heights.
9 . A method of making a semiconductor device assembly, the method comprising:
disposing a plurality of vertical stacks of semiconductor devices on an inner surface of a substrate and extending above the inner surface by a first distance, wherein the plurality of vertical stacks of first semiconductor devices comprises one or more memory dies;
disposing a central interconnect structure between the vertical stacks of semiconductor devices on the inner surface of the substrate and extending above the inner surface by a second distance greater than the first distance, the central interconnect having a plurality of conductors and a sheath of dielectric material that surrounds and electrically isolates each of the plurality of conductors;
electrically coupling each of the plurality of conductors of the central interconnect structure to a corresponding device in the plurality;
disposing a plurality of peripheral interconnect structures around the vertical stacks of semiconductor devices on the inner surface and extending above the inner surface by the second distance;
electrically coupling each of the peripheral interconnect structures to at least one of the semiconductor devices; and
at least partially encapsulating the devices and the interconnects with an encapsulant material,
wherein the encapsulant comprises a different material than the dielectric material, and
wherein the central and peripheral interconnect structures electrically couple the plurality of semiconductor devices to each other, or to an electrically conductive structure disposed at the inner surface of the substrate, or to both.
10 . The method of claim 9 , wherein the semiconductor device assembly is a first semiconductor device subassembly, the substrate is a first substrate, the plurality of vertical stacks of semiconductor devices a first plurality of vertical stacks of semiconductor devices, the central interconnect structure is a first central interconnect structure, the plurality of peripheral interconnect structures is a plurality of first peripheral interconnect structures,
wherein the first substrate forms a first outermost side of the assembly,
wherein the method further comprises:
providing a second semiconductor device subassembly, including:
a second substrate,
a second plurality of vertical stacks of semiconductor devices disposed on a second inner surface of the second substrate,
a second central interconnect structure disposed between the second plurality of vertical stacks of semiconductor devices on the second inner surface,
a plurality of second peripheral interconnect structures disposed around the second plurality of vertical stacks of semiconductor devices on the second inner surface;
at least partially encapsulating the second plurality of vertical stacks of semiconductor devices and interconnects with the encapsulant material; and
coupling at least the first central interconnect structure or a portion of the first peripheral interconnect structures to their respective second interconnect structures, wherein the second substrate forms a second outermost side of the assembly opposite to the first outermost side.