Engineered dielectric profile for high aspect-ratio 3D NAND structures
Methods and apparatus of engineered dielectric profile for high aspect-ratio (AR) 3D NAND structures. The 3D NAND structures comprise a semiconductor structure having multiple stacked memory tiers comprising 2D arrays of memory cells that are charged using vertical structures formed in the semiconductor structure. The memory tiers comprise wordline layers interposed between isolation layers. The vertical structures, such as memory holes or trenches, have a dielectric (e.g., a tunnel dielectric) formed along sidewalls of holes or trenches having a cross-section profile where a thickness of the dielectric at a bottom wordline layer is thicker than the dielectric thickness for at least a portion of wordline layers above the bottom wordline layer. In one example, formation of the tunnel dielectric employs a sandwich design of engineered profile method in which a selective deposition of dielectric is deposited at the bottom sections of the vertical structures while the rest of the structure is un-altered.
1 . A three-dimensional (3D) memory device, comprising:
a plurality of memory tiers comprising wordline layers interposed between isolation layers, a memory tier comprising a two-dimensional (2D) array of memory cells,
a plurality of vertical structures passing through memory cells in the wordline layers and passing through the isolation layers,
a tunnel dielectric, formed over sidewalls of the vertical structures, the tunnel dielectric having a cross-section profile where a first thickness of the tunnel dielectric for a bottom wordline layer is thicker than a second thickness of the tunnel dielectric for at least a portion of the wordline layers disposed above the bottom wordline layer, wherein the first thickness and the second thickness of the tunnel dielectric are measured horizontally.
2 . The 3D memory device of claim 1 , wherein a quality of the tunnel dielectric at the bottom wordline layers matches a quality of the tunnel dielectric for at least one or more of a middle wordline layer and a top wordline layer.
3 . The 3D memory device of claim 1 , wherein the vertical structures comprise memory holes.
4 . The 3D memory device of claim 1 , wherein the vertical structures comprise trenches.
5 . The 3D memory device of claim 1 , wherein the tunnel oxide cross-section profile has a third thickness for a wordline proximate to a top of the vertical structures that substantially matches the first thickness.
6 . The 3D memory structure of claim 1 , wherein the plurality of memory cells comprises floating gate memory cells or Charge-Trap Flash (CTF) memory cells.
7 . A system comprising:
a host, including a processor;
a three-dimensional (3D) NAND memory device, coupled to the host, having,
a plurality of memory tiers comprising wordline layers interposed between isolation layers, a memory tier comprising a two-dimensional (2D) array of memory cells;
a plurality of memory holes passing through memory cells in the wordline layers and passing through the isolation layers;
a dielectric, formed over sidewalls of the memory holes, the dielectric having a cross-section profile on which a first thickness of the dielectric for a bottom wordline layer is thicker than a second thickness of the dielectric for at least a portion of the wordline layers disposed above the bottom wordline layer, wherein the first thickness and the second thickness of the dielectric are measured horizontally.
8 . The system of claim 7 , wherein the memory holes have a depth to diameter aspect ratio of at least 25:1.
9 . The system of claim 7 , wherein the dielectric cross-section profile has a third thickness for a wordline layer proximate to a top of the memory holes that substantially matches the first thickness.
10 . The system of claim 7 , wherein the plurality of memory cells comprises floating gate memory cells or Charge-Trap Flash (CTF) memory cells.
11 . The system of claim 7 , wherein the plurality of memory cells comprises Charge-Trap Flash (CTF) memory cells, and wherein the dielectric comprises at least one of a blocking dielectric layer and a tunnel dielectric layer.