Interconnect layer and method for manufacturing the same
A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes a dielectric layer, an interconnect structure disposed in the dielectric layer, and an etch stop layer which is disposed on a lower end surface of the interconnect structure and which includes silicon carbonitride represented by a general formula of Si x C y N z , wherein x is a silicon content ranging from 30 atomic % to 60 atomic %, y is a carbon content ranging from 25 atomic % to 60 atomic %, z is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of x, y, and z is 100 atomic %.
1 . A semiconductor device comprising:
a substrate; and
an interconnect layer disposed over the substrate and including
a dielectric layer,
an interconnect structure which is disposed in the dielectric layer and which has an upper end surface and a lower end surface, the interconnect structure including a metal line which has the upper end surface,
a liner laterally covering the metal line to separate the metal line from the dielectric layer, the liner being a hermetic layer and including silicon carbonitride represented by a general formula of Si d C e N f , wherein d is a silicon content ranging from 30 atomic % to 60 atomic %, e is a carbon content ranging from 25 atomic % to 60 atomic %, f is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of d, e, and f is 100 atomic %, and
a metal-containing capping portion disposed on the metal line outside of the liner and fully covering the upper end surface of the metal line.
2 . The semiconductor device according to claim 1 , wherein
the interconnect layer further includes a first etch stop layer which is a hermetic layer, which has a flat upper surface directly interfacing the dielectric layer, the liner and the metal line and which includes silicon carbonitride represented by a general formula of Si x C y N z , wherein x is a silicon content ranging from 30 atomic % to 60 atomic %, y is a carbon content ranging from 25 atomic % to 60 atomic %, z is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of x, y, and z is 100 atomic %.
3 . The semiconductor device according to claim 2 , further comprising a second etch stop layer which is a hermetic layer, which is disposed on the dielectric layer to cover the metal line and which includes silicon carbonitride represented by a general formula of Si a C b N c , wherein a is a silicon content ranging from 30 atomic % to 60 atomic %, b is a carbon content ranging from 25 atomic % to 60 atomic %, c is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of a, b, and c is 100 atomic %,
wherein the second etch stop layer covers the metal-containing capping portion and interfaces the liner, the second etch stop layer including:
a first etch stop layer portion directly interfacing a portion of the dielectric layer and having an upper surface distal from the portion of the dielectric layer, and
a second etch stop portion directly interfacing the liner and the metal-containing capping portion and having an upper surface distal from the metal-containing capping portion, a distance between the upper surface of the first etch stop layer portion and an upper surface of the portion of the dielectric layer being less than a distance between the upper surface of the second etch stop layer potion and the upper end surface of the metal line.
4 . The semiconductor device according to claim 1 , wherein the silicon carbonitride represented by the general formula of Si d C e N f has a k-value ranging from 2.5 to 4.5 and a breakdown field ranging from 4 MV/cm to 6 MV/cm.
5 . The semiconductor device according to claim 2 , wherein the silicon carbonitride represented by the general formula of Si x C y N z has a k-value ranging from 2.5 to 4.5 and a breakdown field ranging from 4 MV/cm to 6 MV/cm.
6 . The semiconductor device according to claim 3 , wherein the silicon carbonitride represented by the general formula of Si a C b N c has a k-value ranging from 2.5 to 4.5 and a breakdown field ranging from 4 MV/cm to 6 MV/cm.
7 . The semiconductor device according to claim 2 , wherein values of x, y, and z in the general formula of SixCyNz are the same as values of the d, e, and f in the general formula of Si d C e N f , respectively.
8 . The semiconductor device according to claim 3 , wherein values of a, b, and c in the general formula of Si a C b N c are the same as values of the d, e, and f in the general formula of Si d C e N f , respectively.
9 . The semiconductor device according to claim 3 , wherein values of a, b, and c in the general formula of Si a C b N c are the same as values of the x, y, and e in the general formula of Si x C y N z , respectively.
10 . The semiconductor device according to claim 1 , wherein
the dielectric layer has a lower surface and an upper surface which are proximate to and distal from the substrate, respectively,
the liner and the metal line extend from the upper surface of the dielectric layer and terminate at the lower surface of the dielectric layer, and
the liner has an upper end surface flush with the upper end surface of the metal line and a lower end surface flush with a lower end surface of the metal line.
11 . The semiconductor device according to claim 1 , wherein the dielectric layer has a lower surface and an upper surface which are proximate to and distal from the substrate, respectively, and
the upper end surface of the metal line is flush with the upper surface of the dielectric layer.
12 . The semiconductor device according to claim 10 , wherein the liner interfaces the first etch stop layer and is free of interfacing the metal-containing capping portion.
13 . A semiconductor device comprising:
a substrate; and
an interconnect layer disposed over the substrate and including
a dielectric layer having a lower surface and an upper surface which are proximate to and distal from the substrate, respectively,
an interconnect structure which is disposed in the dielectric layer and which has an upper end surface and a lower end surface respectively flush with the upper surface and the lower surface of the dielectric layer, the interconnect structure including a metal line which has the upper end surface,
a first etch stop layer which is a hermetic layer, which is disposed on the lower end surface of the interconnect structure and which includes silicon carbonitride represented by a general formula of Si x C y N z , wherein x is a silicon content ranging from 30 atomic % to 60 atomic %, y is a carbon content ranging from 25 atomic % to 60 atomic %, z is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of x, y, and z is 100 atomic %, and
a liner laterally covering the metal line to separate the metal line from the dielectric layer, the liner being a hermetic layer and including silicon carbonitride represented by a general formula of Si d C e N f , wherein d is a silicon content ranging from 30 atomic % to 60 atomic %, e is a carbon content ranging from 25 atomic % to 60 atomic %, f is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of d, e, and f is 100 atomic %,
wherein
the liner and the metal line extend from the upper surface of the dielectric layer and terminate at the lower surface of the dielectric layer,
the metal line includes a lower metal line portion and an upper metal line portion integrated with each other and including a same material, and
the first etch stop layer directly interfaces the dielectric layer, the liner and the lower metal line portion of the metal line.
14 . The semiconductor device according to claim 13 , further comprising a second etch stop layer which is a hermetic layer, which is disposed on the interconnect layer to cover the upper end surface of the interconnect structure and which includes silicon carbonitride represented by a general formula of SiaCbNc, wherein a is a silicon content ranging from 30 atomic % to 60 atomic %, b is a carbon content ranging from 25 atomic % to 60 atomic %, c is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of a, b, and c is 100 atomic %,
wherein the second etch stop layer includes:
a first etch stop layer portion directly interfacing a portion of the dielectric layer and having an upper surface distal from the portion of the dielectric layer, and
a second etch stop layer portion directly interfacing the liner and having an upper surface distal from the metal line, the upper surface of the first etch stop layer portion being not flush with the upper surface of the second etch stop layer potion.
15 . The semiconductor device according to claim 13 , wherein the silicon carbonitride represented by the general formula of Si x C y N z has a k-value ranging from 2.5 to 4.5 and a breakdown field ranging from 4 MV/cm to 6 MV/cm.
16 . The semiconductor device according to claim 14 , wherein the silicon carbonitride represented by the general formula of Si a C b N c has a k-value ranging from 2.5 to 4.5 and a breakdown field ranging from 4 MV/cm to 6 MV/cm.
17 . The semiconductor device according to claim 13 , further comprising a stack assembly which is disposed on the dielectric layer and which includes two third etch stop layers and a fourth etch stop layer sandwiched between the two third etch stop layers, wherein each of the two third etch stop layers includes aluminum oxide, aluminum nitride, aluminum oxynitride, or combinations thereof, wherein the fourth etch stop layer includes silicon oxycarbide, and wherein one of the two third etch stop layers adjacent to the dielectric layer includes:
a first etch stop layer portion disposed on a portion of the dielectric layer and directly interfacing the fourth etch stop layer at a first interface, and
a second etch stop layer portion disposed over the metal line and directly interfacing the fourth etch stop layer at a second interface, which is not flush with the first interface.
18 . A method for manufacturing a semiconductor device, comprising:
forming an interconnect structure in a dielectric layer disposed over a substrate, wherein the interconnect structure includes a metal line;
forming a liner laterally covering the metal line to separate the metal line from the dielectric layer, the liner being a hermetic layer and including silicon carbonitride represented by a general formula of Si d C e N f , wherein d is a silicon content ranging from 30 atomic % to 60 atomic %, e is a carbon content ranging from 25 atomic % to 60 atomic %, f is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of d, e, and f is 100 atomic %; and
forming a metal-containing capping portion on the metal line outside of the liner so as to fully cover an upper end surface of the metal line,
wherein the liner has an upper end surface flush with the upper end surface of the metal line and a lower end surface flush with a lower end surface of the metal line.
19 . The method according to claim 18 , further comprising forming a first etch stop layer on an lower end surface of the interconnect structure, the first etch stop layer being a hermetic layer and including silicon carbonitride represented by a general formula of Si x C y N z , wherein x is a silicon content ranging from 30 atomic % to 60 atomic %, y is a carbon content ranging from 25 atomic % to 60 atomic %, z is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of x, y, and z is 100 atomic %.
20 . The method according to claim 19 , further comprising forming a second etch stop layer on an upper end surface of the interconnect structure, the second etch stop layer being a hermetic layer and including silicon carbonitride represented by a general formula of Si a C b N c , wherein a is a silicon content ranging from 30 atomic % to 60 atomic %, b is a carbon content ranging from 25 atomic % to 60 atomic %, c is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of a, b, and c is 100 atomic %.