Semiconductor package

1 . A semiconductor package comprising:

a first circuit element;

a first semiconductor chip flip-chip bonded to a top surface of the first circuit element;

an insulating plate on the first circuit element, the insulating plate having a first through hole and a second through hole, the first through hole exposing the first semiconductor chip, the second through hole on one side of the insulating plate and spaced apart from the first semiconductor chip;

a connection member in the second through hole and electrically connected to the first circuit element;

a second circuit element on the connection member and the insulating plate, the second circuit element being electrically connected to the connection member;

a second semiconductor chip, the second semiconductor chip being spaced apart from the first semiconductor chip in the first through hole and flip-chip bonded to a bottom surface of the second circuit element;

a fluid layer in the first through hole between the first semiconductor chip and the second semiconductor chip;

a first heat dissipation structure having a plurality of first patterns that are laterally spaced apart from each other on an upper portion of the first semiconductor chip;

a second heat dissipation structure having a plurality of second patterns that are laterally spaced apart from each other on a lower portion of the second semiconductor chip; and

an adhesive layer bonding some of the plurality of first patterns to some of the plurality of second patterns, wherein

the plurality of first patterns are spaced apart from the plurality of second patterns with the fluid layer therebetween, and

a vertical gap spacing between the plurality of first patterns and the plurality of second patterns corresponds to a thickness of the adhesive layer.

2 . The semiconductor package of claim 1 , wherein

the first circuit element comprises a first package substrate, and

the second circuit element comprises a redistribution level layer.

3 . The semiconductor package of claim 1 , wherein

the first circuit element comprises a first package substrate, and the second circuit element comprises a second package substrate.

4 . The semiconductor package of claim 1 , wherein

the adhesive layer includes a first adhesive portion spaced apart laterally from a second adhesive portion,

the some of the plurality of first patterns include a first outermost first pattern and a second outermost first pattern that respectively are laterally spaced apart from each other on a first end of the upper portion of the first semiconductor chip and a second end of the upper portion of the first semiconductor chip,

the some of the plurality of second patterns include a first outermost second pattern and a second outermost second pattern that respectively are laterally spaced apart from each other on a first end of the lower portion of the second semiconductor chip and a second end of the lower portion of the first semiconductor chip,

the first adhesive portion connects the first outermost first pattern to the first outermost second pattern, and

the second adhesive portion connects the second outermost first pattern to the second outermost second pattern.

5 . The semiconductor package of claim 1 , wherein the fluid layer contacts the first heat dissipation structure and the second heat dissipation structure.

6 . The semiconductor package of claim 1 , wherein

the insulating plate comprises a fluid inlet and a fluid outlet,

the fluid outlet is opposite the fluid inlet and in fluid communication with the fluid inlet,

the fluid inlet and the fluid outlet are in a flow path for supplying a fluid between the first semiconductor chip and the second semiconductor chip in a planar view and for discharging the fluid.

7 . The semiconductor package of claim 6 , further comprising:

a fluid circulation device connected to the fluid inlet and the fluid outlet, wherein

the fluid circulation device is in fluid communication with the fluid inlet and the fluid outlet, and

the fluid circulation device is configured to circulate the fluid between the first semiconductor chip and the second semiconductor chip.

8 . The semiconductor package of claim 6 , further comprising:

a first sealing portion and a second sealing portion in the fluid inlet and the fluid outlet, respectively, wherein

the first sealing portion and the second sealing portion are configured to limit a loss of the fluid if the fluid is supplied between the first semiconductor chip and the second semiconductor chip, respectively.

9 . The semiconductor package of claim 1 , wherein

the connection member comprises a column-like member.

10 . A semiconductor package comprising:

a first circuit element;

a first semiconductor chip flip-chip bonded to a top surface of the first circuit element;

a first heat dissipation structure on a rear surface of the first semiconductor chip, the first heat dissipation structure including a plurality of first patterns spaced apart from each other on the rear surface of the first semiconductor chip;

an insulating plate on the first circuit element, the insulating plate having a first through hole and a second through hole, the first through hole exposing the first semiconductor chip, the second through hole on one side of the insulating plate and spaced apart from the first semiconductor chip;

a connection member in the second through hole and electrically connected to the first circuit element;

a second circuit element on the connection member and the insulating plate, the second circuit element electrically connected to the connection member;

a second semiconductor chip, the second semiconductor chip being spaced apart from the first semiconductor chip in the first through hole and flip-chip bonded to a bottom surface of the second circuit element;

a second heat dissipation structure on a rear surface of the second semiconductor chip, the second heat dissipation structure including a plurality of second patterns spaced apart from each other on the rear surface of the second semiconductor chip;

an adhesive layer bonding some of the plurality of first patterns to some of the plurality of second patterns; and

a fluid layer between the first heat dissipation structure and the second heat dissipation structure in the first through hole, wherein

a vertical gap spacing between the plurality of first patterns and the plurality of second patterns corresponds to a thickness of the adhesive layer.

11 . The semiconductor package of claim 10 , wherein the fluid layer contacts the plurality of first patterns and the plurality of second patterns.

12 . The semiconductor package of claim 10 , wherein

the insulating plate comprises a fluid inlet and a fluid outlet,

the fluid outlet is opposite the fluid inlet and in fluid communication with the fluid inlet,

the fluid inlet and the fluid outlet are in a flow path for supplying a fluid between the first heat dissipation structure and the second heat dissipation structure in a planar view and for discharging the fluid.

13 . The semiconductor package of claim 12 , further comprising:

a fluid circulation device connected to the fluid inlet and the fluid outlet, wherein

the fluid circulation device is in fluid communication with the fluid inlet and the fluid outlet, and

the fluid circulation device is configured to circulate the fluid between the first heat dissipation structure and the second heat dissipation structure.

14 . The semiconductor package of claim 13 , wherein the fluid circulation device includes a fluid supply structure connected to the fluid inlet, a fluid storage connected to the fluid outlet, and a pump connected to the fluid supply structure and the fluid storage.

15 . The semiconductor package of claim 12 , further comprising:

a first sealing portion and a second sealing portion in the fluid inlet and the fluid outlet, respectively, wherein

the first sealing portion and the second sealing portion are configured to limit loss of the fluid supplied between the first heat dissipation structure and the second heat dissipation structure, respectively.

16 . A semiconductor package comprising:

a first circuit element including a first package substrate;

a first semiconductor chip electrically connected to the first circuit element through first chip connection balls, the first semiconductor chip including a first chip body and the first chip connection balls, the first chip body including a first front surface and a first rear surface opposite the first front surface, the first chip connection balls being on the first front surface of the first chip body;

a first heat dissipation structure including a plurality of first patterns on the first rear surface of the first semiconductor chip and spaced apart from each other;

an insulating plate on the first circuit element, the insulating plate having a first through hole and a second through hole, the first through hole exposing the first semiconductor chip, the second through hole on one side of the insulating plate and spaced apart from the first semiconductor chip;

a connection member in the second through hole and electrically connected to the first circuit element;

a second circuit element on the connection member and the insulating plate, the second circuit element being electrically connected to the connection member, and the second circuit element including a redistribution level layer;

a second semiconductor chip electrically connected to the second circuit element through second chip connection balls,

the second semiconductor chip being spaced apart from the first semiconductor chip in the first through hole,

the second semiconductor chip including a second chip body and the second chip connection balls, the second chip body having a second front surface and a second rear surface opposite the second front surface, the second chip connection balls being on the second rear surface of the second chip body, and the second semiconductor chip being spaced apart from the first semiconductor chip in the first through hole;

a second heat dissipation structure on a second rear surface of the second semiconductor chip, the second heat dissipation structure including a plurality of second patterns on the second rear surface of the second semiconductor chip and spaced apart from each other; and

an adhesive layer bonding some of the plurality of first patterns to some of the plurality of second patterns; and

a fluid layer between the first heat dissipation structure and the second heat dissipation structure in the first through hole, wherein

a vertical gap spacing between the plurality of first patterns and the plurality of second patterns corresponds to a thickness of the adhesive layer.

17 . The semiconductor package of claim 16 , further comprising:

a fluid circulation device, wherein

the insulating plate comprises a fluid inlet and a fluid outlet,

the fluid outlet is opposite the fluid inlet and in fluid communication with the fluid inlet,

the fluid inlet and the fluid outlet are in a flow path for supplying a fluid between the first heat dissipation structure and the second heat dissipation structure in a planar view and for discharging the fluid, and

the fluid circulation device is configured to circulate the fluid between the first heat dissipation structure and the second heat dissipation structure.

18 . The semiconductor package of claim 16 , wherein

a thickness of the insulating plate is greater than a total thickness, and

the total thickness is a sum of a thickness of the first chip body, a thickness of the second chip body, and a separation distance between the first chip body and the second chip body.

19 . The semiconductor package of claim 16 , wherein

a thickness of the insulating plate is equal to a total thickness, and

the total thickness is a sum of a thickness of the first chip body, a thickness of the second chip body, and a separation distance between the first chip body and the second chip body.