IP Library Granted Patent US 12,713,912
Granted Patent B2
US 12,713,912 · App. 18/379,286 · Granted Aug 18, 2026

Semiconductor package

Inventors: Sunggu Kang (Suwon-si, KR); Jae Choon Kim (Suwon-si, KR); Sung-Ho Mun (Suwon-si, KR); Hwanjoo Park (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10W40/22H10W40/251H10W70/685H10W74/016H10W90/701H10W72/877H10W74/00H10W90/724H10W90/732H10W90/734
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Quick Facts
Patent No.
US 12,713,912
App. No.
18/379,286
Granted
Aug 18, 2026
Kind
B2
Abstract

A semiconductor package includes a redistribution layer structure, a semiconductor structure on the redistribution layer structure, at least one heat dissipation structure on the semiconductor structure, where the at least one heat dissipation structure may include a first epoxy molding compound, a molding material for molding the semiconductor structure and the at least one heat dissipation structure, on the redistribution layer structure, where the molding material may include a second epoxy molding compound, where the first epoxy molding compound may have higher thermal conductivity than the second epoxy molding compound.

Claims (45)

1 . A semiconductor package comprising:

a redistribution layer structure;

a semiconductor structure on the redistribution layer structure, the semiconductor structure comprising a first semiconductor die and a second semiconductor die on the first semiconductor die;

at least one heat dissipation structure on the first semiconductor die and around the second semiconductor die, wherein the at least one heat dissipation structure comprises a first epoxy molding compound; and

a molding material on the redistribution layer structure and around the semiconductor structure and the at least one heat dissipation structure,

wherein the molding material comprises a second epoxy molding compound,

wherein a first thermal conductivity of the first epoxy molding compound is higher than a second thermal conductivity of the second epoxy molding compound.

2 . The semiconductor package of claim 1 , wherein the first epoxy molding compound comprises a metal filler.

3 . The semiconductor package of claim 1 , wherein the first epoxy molding compound comprises a ceramic filler.

4 . The semiconductor package of claim 1 , wherein the first epoxy molding compound comprises a carbon filler.

5 . The semiconductor package of claim 1 , wherein a first level of a first upper surface of each heat dissipation structure among the at least one heat dissipation structure and a second level of a second upper surface of the molding material are a same level.

6 . The semiconductor package of claim 1 , wherein, in a plan view, each heat dissipation structure among the at least one heat dissipation structure has a dot, elongated, elliptical, circular, or polygonal shape.

7 . The semiconductor package of claim 1 , wherein the at least one heat dissipation structure comprises heat dissipation structures spaced apart from each other at regular intervals.

8 . The semiconductor package of claim 1 , wherein:

at least one of the at least one heat dissipation structure comprises the first epoxy molding compound;

each of remaining heat dissipation structures among the at least one heat dissipation structure comprises an additional epoxy molding compound; and

a third thermal conductivity of the additional epoxy molding compound is higher than the second thermal conductivity of the second epoxy molding compound.

9 . The semiconductor package of claim 8 , wherein the semiconductor structure comprises an asymmetric structure.

10 . The semiconductor package of claim 1 , wherein the semiconductor structure comprises a three-dimensional integrated circuit structure.

11 . The semiconductor package of claim 10 , wherein each heat dissipation structure among the at least one heat dissipation structure is on at least one of the first semiconductor die or the second semiconductor die.

12 . The semiconductor package of claim 11 , wherein a heat dissipation structure of the at least one heat dissipation structure on the first semiconductor die is disposed around the second semiconductor die.

13 . The semiconductor package of claim 11 , wherein a heat dissipation structure of the at least one heat dissipation structure on the first semiconductor die comprises a through opening, and the second semiconductor die is in the through opening.

14 . The semiconductor package of claim 11 , wherein, in a plan view, the heat dissipation structure disposed on the second semiconductor die has a shape obtained by scaling the shape of the second semiconductor die.

15 . A semiconductor package comprising:

a redistribution layer structure;

a first semiconductor structure on the redistribution layer structure;

a second semiconductor structure side by side with the first semiconductor structure on the redistribution layer structure;

at least one heat dissipation structure on the first semiconductor structure and comprising a through opening therein, wherein the at least one heat dissipation structure comprises a first epoxy molding compound; and

a molding material on the redistribution layer structure and around the first semiconductor structure, the second semiconductor structure, and the at least one heat dissipation structure,

wherein the molding material comprises a second epoxy molding compound,

wherein a first thermal conductivity of the first epoxy molding compound is higher than a second thermal conductivity of the second epoxy molding compound.

16 . The semiconductor package of claim 15 , wherein a side surface of each heat dissipation structure among the at least one heat dissipation structure is in contact with the first semiconductor structure, and another side surface is exposed to an outside.

17 . A semiconductor package comprising:

a front side redistribution layer structure;

a first semiconductor structure on the front side redistribution layer structure, the first semiconductor structure comprising a first semiconductor die and a second semiconductor die on the first semiconductor die;

at least one heat dissipation structure on the first semiconductor die and around the second semiconductor die, wherein the at least one heat dissipation structure comprises a first epoxy molding compound;

a plurality of conductive posts electrically connected to the front side redistribution layer structure on the front side redistribution layer structure;

a molding material on the front side redistribution layer structure and around the first semiconductor structure, the at least one heat dissipation structure, and the plurality of conductive posts,

wherein the molding material comprises a second epoxy molding compound;

a back side redistribution layer structure on the plurality of conductive posts and the molding material, and electrically connected to the plurality of conductive posts; and

a second semiconductor structure on the back side redistribution layer structure,

wherein a first thermal conductivity of the first epoxy molding compound is higher than a second thermal conductivity of the second epoxy molding compound.

18 . The semiconductor package of claim 17 , wherein a side surface of each heat dissipation structure among the at least one heat dissipation structure is in contact with the first semiconductor structure, and another side surface is in contact with the back side redistribution layer structure.

19 . The semiconductor package of claim 17 , wherein the first semiconductor structure comprises a system-on-chip (SOC).

20 . The semiconductor package of claim 17 , wherein the second semiconductor structure comprises a DRAM or high bandwidth memory semiconductor (HBM).