IP Library Granted Patent US 12,713,919
Granted Patent B2
US 12,713,919 · App. 17/993,797 · Granted Aug 18, 2026

Semiconductor package structure

Inventors: Hung-Hsien Huang (Kaohsiung, TW); Wen Chun Wu (Kaohsiung, TW); Chih-Pin Hung (Kaohsiung, TW)
Assignee: Advanced Semiconductor Engineering, Inc.
H10W40/73H10W40/40H10W40/235H10W40/258H10W72/877H10W74/111H10W74/114H10W76/15H10W90/00H10W90/724H10W90/736
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Quick Facts
Patent No.
US 12,713,919
App. No.
17/993,797
Granted
Aug 18, 2026
Kind
B2
Abstract

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes at least one electronic component, a heat source, and a heat dissipation element. The heat source is adjacent to the electronic component. The heat dissipation element is disposed adjacent to the heat source and the electronic component. The heat dissipation element includes a heat transmitting structure configured to reduce heat, which is from the heat source, through the heat dissipation element, and transmitting in a direction toward the electronic component.

Claims (50)

1 . A semiconductor package structure, comprising:

at least one electronic component;

a heat source adjacent to the electronic component; and

a heat dissipation element disposed adjacent to the heat source and the electronic component, the heat dissipation element comprising a heat transmitting structure configured to reduce heat which is from the heat source, through the heat dissipation element, and transmitting in a direction toward the electronic component, wherein the heat transmitting structure comprises:

a plurality of protrusions;

one or more dendritic structures disposed on surfaces of the plurality of protrusions, wherein the one or more dendritic structures comprise:

a plurality of trunks;

a plurality of first branches grown from the trunks; and

a plurality of second branches grown from the first branches, wherein the plurality of first branches and the plurality of second branches extend toward at least two different directions, wherein interfaces exist between the one or more dendritic structures and inner surfaces and bottom surfaces of the plurality of protrusions, and

wherein the heat transmitting structure is located over the heat source, and the heat transmitting structure is configured to dissipate heat upwards faster than in lateral directions.

2 . The semiconductor package structure as claimed in claim 1 , wherein the heat transmitting structure is an anisotropic heat conducting zone surrounded by an isotropic heat conducting zone of the heat dissipation element, wherein the anisotropic heat conducting zone has a coefficient of planar heat conduction (k x-y ) around 10-15 times greater than that of the isotropic heat conducting zone.

3 . The semiconductor package structure as claimed in claim 2 , wherein the anisotropic heat conducting zone is configured to confine the heat transferred from the heat source within a region above the heat source.

4 . The semiconductor package structure as claimed in claim 1 , wherein the heat transmitting structure is surrounded by the at least one electronic component and not overlapped by the at least one electronic component from a top view perspective.

5 . The semiconductor package structure as claimed in claim 2 , wherein the coefficient of planar heat conduction (k x-y ) of the anisotropic heat conducting zone is about 4500-5500 W/mk, and the coefficient of planar heat conduction (k x-y ) of the isotropic heat conducting zone about 300-450 W/mk.

6 . The semiconductor package structure as claimed in claim 1 , wherein the heat transmitting structure comprises a chamber entirely overlapping the heat source from a top view perspective, wherein a plurality of inter-dendritic pores between or among two or more dendritic structures are in the chamber.

7 . The semiconductor package structure as claimed in claim 6 , wherein a plurality of intra-dendritic pores defined by the trunks and the first branches are in the chamber.

8 . The semiconductor package structure as claimed in claim 7 , wherein the inter-dendritic pores have a size greater than that of the intra-dendritic pores.

9 . The semiconductor package structure as claimed in claim 7 , wherein the intra-dendritic pores enhance capillary force within the one or more dendritic structures and the inter-dendritic pores provide fluid channels with a reduced flow resistance in the chamber.

10 . The semiconductor package structure as claimed in claim 1 , wherein the interfaces include a first interface extending in a first direction and a second interface extending in a second direction perpendicular to the first direction.

11 . The semiconductor package structure as claimed in claim 10 , wherein the first interface is not overlapped by the second interface along the first direction and the second direction.

12 . The semiconductor package structure as claimed in claim 2 , wherein a first top surface of the anisotropic heat conducting zone and a second top surface of the isotropic heat conducting zone are coplanar.

13 . The semiconductor package structure as claimed in claim 12 , further comprising a thermal interface material (TIM) layer in direct contact with the anisotropic heat conducting zone.

14 . A semiconductor package structure, comprising:

a heat source;

a heat dissipation element attached to the heat source, wherein the heat dissipation element comprises a heat transmitting portion and a heat dissipating portion, and the heat transmitting portion is configured to reduce a first expansion of the heat dissipating portion caused by the heat dissipating portion absorbing heat generated by the heat source, wherein the heat transmitting portion comprises:

a plurality of protrusions;

one or more dendritic structures disposed on surfaces of the plurality of protrusions, wherein the one or more dendritic structures comprise:

a plurality of trunks;

a plurality of first branches grown from the trunks; and

a plurality of second branches grown from the first branches, wherein the plurality of first branches and the plurality of second branches extend toward at least two different directions, wherein interfaces exist between the one or more dendritic structures and inner surfaces and bottom surfaces of the plurality of protrusions; and

a heat sink disposed over the heat dissipation element,

wherein the heat transmitting portion is located over the heat source, and the heat transmitting portion is configured to dissipate heat in a direction from the heat source toward the heat sink.

15 . The semiconductor package structure as claimed in claim 14 , further comprising:

a thermal interface material (TIM) layer between the heat source and the heat transmitting portion, wherein the TIM layer is in direct contact with the heat transmitting portion.

16 . The semiconductor package structure as claimed in claim 14 , further comprising:

at least one electronic component disposed adjacent to the heat source, wherein the heat transmitting portion is located over the heat source, and the heat transmitting portion is an anisotropic heat conducting zone configured to conduct the heat upwards faster than in the direction toward the at least one electronic component, and wherein the anisotropic heat conducting zone is configured to confine the heat transferred from the heat source within a region above the heat source.

17 . The semiconductor package structure as claimed in claim 14 , wherein the heat transmitting portion comprises a chamber, wherein the chamber entirely overlaps the heat source from a top view perspective, wherein a plurality of inter-dendritic pores between or among two or more dendritic structures are in the chamber, wherein a plurality of intra-dendritic pores defined by the trunks and the first branches are in the chamber, and wherein the inter-dendritic pores have a size greater than that of the intra-dendritic pores.

18 . The semiconductor package structure as claimed in claim 14 , wherein the heat dissipating portion is composed of a continuous portion of the heat dissipation element and the heat transmitting portion extends from an upper surface of the heat dissipating portion to a lower surface of the heat dissipating portion, wherein a first top surface of the heat transmitting portion and a second top surface of the heat dissipating portion are coplanar.

19 . The semiconductor package structure as claimed in claim 16 , wherein the anisotropic heat conducting zone is surrounded by the at least one electronic component and not overlapped by the at least one electronic component from a top view perspective.

20 . A semiconductor package structure, comprising:

a first electronic component;

a heat source adjacent to the first electronic component;

a heat dissipation element disposed over the first electronic component and the heat source, wherein the heat dissipation element comprises a heat transmitting structure over the heat source, and the heat transmitting structure is free from overlapping the first electronic component from a top view perspective, wherein the heat transmitting structure comprises:

a plurality of protrusions;

one or more dendritic structures disposed on surfaces of the plurality of protrusions, wherein the one or more dendritic structures comprise:

a plurality of trunks;

a plurality of first branches grown from the trunks; and

a plurality of second branches grown from the first branches, wherein the plurality of first branches and the plurality of second branches extend toward at least two different directions, wherein interfaces exist between the one or more dendritic structures and inner surfaces and bottom surfaces of the plurality of protrusions; and

a substrate, to which the heat source is attached,

wherein the heat transmitting structure is located over the heat source, and the heat transmitting structure is configured to dissipate heat in a direction perpendicular to an upper surface of the substrate.