Power semiconductor module arrangement comprising heat-conducting layer and heat sink and method for producing the same
A power semiconductor module arrangement includes a power semiconductor module, wherein the power semiconductor module includes a substrate for carrying at least one semiconductor body, and a heat-conducting layer arranged on a lower surface of the power semiconductor module, wherein the lower surface of the power semiconductor module is a surface that is configured to be mounted to a heat sink, and wherein the heat-conducting layer consists of a metallic and non-eutectic material that is solid at temperatures below a first threshold temperature, that is viscous at temperatures above the first threshold temperature and below a second threshold temperature, and that is fluid at temperatures above the second threshold temperature.
1 . A power semiconductor module arrangement comprising a power semiconductor module, wherein the power semiconductor module comprises:
a substrate for carrying at least one semiconductor body; and
a heat-conducting layer arranged on a lower surface of the power semiconductor module, wherein the lower surface of the power semiconductor module is a surface that is configured to be mounted to a heat sink, wherein
the heat-conducting layer consists of a metallic and non-eutectic material that is solid at temperatures below a first threshold temperature, that is viscous at temperatures above the first threshold temperature and below a second threshold temperature, and that is fluid at temperatures above the second threshold temperature.
2 . The power semiconductor module arrangement of claim 1 , wherein the substrate comprises a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer, the first metallization layer configured to carry the at least one semiconductor body.
3 . The power semiconductor module arrangement of claim 1 , wherein the lower surface of the power semiconductor module is formed by a surface of the substrate.
4 . The power semiconductor module arrangement of claim 1 , wherein the power semiconductor module further comprises a base plate, wherein the substrate is arranged on a first surface of the base plate and the lower surface of the power semiconductor module is formed by a second surface of the base plate opposite the first surface.
5 . The power semiconductor module arrangement of claim 1 , further comprising a heat sink, wherein the heat-conducting layer is arranged between the power semiconductor module and the heat sink, and permanently attaches the heat sink to the power semiconductor module.
6 . The power semiconductor module arrangement of claim 1 , wherein the first threshold temperature is between 80° C. and 125° C.
7 . The power semiconductor module arrangement of claim 1 , wherein the second threshold temperature is between 140° C. and 180° C.
8 . The power semiconductor module arrangement of claim 1 , wherein the heat-conducting layer consists of a metal alloy.
9 . The power semiconductor module arrangement of claim 1 , wherein the heat-conducting layer undergoes at least one phase change from solid to viscous or solid to liquid when heating up from room temperature to an operating temperature of the power semiconductor module.
10 . The power semiconductor module arrangement of claim 9 , wherein the heat-conducting layer comprises tin.
11 . The power semiconductor module arrangement of claim 10 , wherein the heat-conducting layer comprises between 50 and 55 weight % of tin.
12 . The power semiconductor module arrangement of claim 7 , wherein the heat-conducting layer consists of an alloy comprising more than 10 weight % tin and less than 90 weight % of additional metals selected from the group of indium, bismuth, antimony, silver, and lead.