Semiconductor device and method of manufacturing a semiconductor device

1 . A semiconductor device, comprising:

a substrate;

an isolation region at a first main surface of the substrate, wherein the isolation region comprises a lower portion and an upper portion protruding from the lower portion;

a charge shielding layer over at least a part of the upper portion of the isolation region, wherein an edge of the charge shielding layer has a sidewall which slopes inward at a first angle of equal to or less than 50 degrees; and

a metal barrier layer over at least a part of the charge shielding layer and over at least a part of the lower portion of the isolation region.

2 . The semiconductor device of claim 1 , wherein the lower portion of the isolation region is not covered by the charge shielding layer.

3 . The semiconductor device of claim 1 , wherein the charge shielding layer is directly on the at least a part of the upper portion of the isolation region.

4 . The semiconductor device of claim 1 , wherein the charge shielding layer comprises at least one of nitride, oxide and aluminum.

5 . The semiconductor device of claim 1 , wherein the charge shielding layer is at least two times as thick as the upper portion of the isolation region.

6 . The semiconductor device of claim 1 , wherein the metal barrier layer comprises a stack of layers.

7 . The semiconductor device of claim 1 , further comprising a metal layer over at least a part of the metal barrier layer, wherein the metal layer comprises copper.

8 . The semiconductor device of claim 1 , wherein an edge of the upper portion of the isolation region has a sidewall which slopes inward at a second angle between 35 degrees and 90 degrees.

9 . The semiconductor device of claim 1 , wherein the isolation region comprises silicon dioxide.

10 . The semiconductor device of claim 1 , further comprising a passivation layer over the charge shielding layer.

11 . The semiconductor device of claim 1 , wherein the semiconductor device is a power semiconductor device and further comprises:

an active region comprising at least one active device configured to conduct a load current between the first main surface of the substrate and a second main surface of the substrate; and

an edge termination region arranged between the active region and an edge of the power semiconductor device, wherein the charge shielding layer is disposed in the edge termination region.

12 . A method of manufacturing a semiconductor device, the method comprising:

forming an isolation region at a main surface of a substrate;

forming a charge shielding layer over the isolation region;

etching the charge shielding layer to form an edge that has a sidewall which slopes inward at a first angle of equal to or less than 50 degrees;

etching the isolation region to form an upper portion of the isolation region protruding from a lower portion of the isolation region; and

forming a metal barrier layer over the charge shielding layer and over the isolation region.

13 . The method of claim 12 , wherein etching the charge shielding layer and etching the isolation region are performed in a common etching step.

14 . The method of claim 12 , further comprising:

forming a metal layer over at least a part of the metal barrier layer; and

etching at least the metal barrier layer to expose a part of the charge shielding layer.

15 . The method of claim 14 , further comprising:

forming a passivation layer at least over the exposed part of the charge shielding layer and over at least a part of the metal layer.

16 . The method of claim 12 , wherein etching the isolation region to form the upper portion protruding from the lower portion of the isolation region comprises forming an edge of the upper portion of isolation region having a sidewall which slopes inward at a second angle between 35 degrees and 90 degrees.

17 . The method of claim 12 , wherein the charge shielding layer comprises at least one of nitride, oxide and aluminum.

18 . The method of claim 12 , wherein the charge shielding layer is formed directly on the isolation region.

19 . The method of claim 12 , wherein the metal barrier layer comprises a stack of layers.

20 . The method of claim 12 , wherein the isolation region comprises silicon dioxide.