Method for processing a semiconductor wafer and semiconductor composite structure
A method for processing a semiconductor wafer is proposed. The method may include: reducing a thickness of the semiconductor wafer; before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer; and after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.
1 . A method for processing a semiconductor wafer, the method comprising:
reducing a thickness of the semiconductor wafer;
before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer; and
after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side,
wherein reducing the thickness of the semiconductor wafer comprises thinning the semiconductor wafer by at least one of grinding, laser ablation, etching the semiconductor wafer, and splitting the semiconductor wafer along a splitting region,
wherein the splitting region comprises a splitting layer comprising at least one of silicon germanium, silicon oxide, graphite, molybdenum and silicon nitride, or the splitting region is a region of porous semiconductor material and/or a region comprising voids.
2 . The method of claim 1 , wherein the support structure is attached to the second side of the semiconductor wafer by at least one of: gluing, bonding, adhesive bonding, laser melting, laser bonding, and soldering.
3 . The method of claim 1 , wherein the support structure is deposited at the second side of the semiconductor wafer with a three-dimensional (3D) printing process.
4 . The method of claim 1 , wherein the support structure comprises at least one of glass, sapphire, silicon, ceramic, carbon, plastic, and metal.
5 . The method of claim 1 , wherein a cross-sectional area of the support structure comprises an inner step, wherein the semiconductor wafer is located on the inner step after providing the support structure.
6 . The method of claim 1 , wherein an outer diameter of the support structure differs from a diameter of the semiconductor wafer by at most ±1% of the diameter of a semiconductor wafer.
7 . The method of claim 1 , wherein, in a cross-section, the support structure has a maximum height of at most 3 mm and at least 0.1 mm and/or a maximum width of at most 50 mm and at least 3 mm.
8 . The method of claim 1 , wherein a thickness of the semiconductor wafer is at most 300 μm after reducing the thickness of the semiconductor wafer.
9 . The method of claim 1 , further comprising:
forming at least a part of at least one electrical element structure on the semiconductor wafer; and/or
performing electrical testing of the at least one electrical element structure formed on the semiconductor wafer while the semiconductor wafer is mechanically supported by the support structure.
10 . The method of claim 1 , further comprising:
before reducing the thickness of the semiconductor wafer, forming an epitaxial semiconductor layer on the first side of the semiconductor wafer.
11 . The method of claim 1 , further comprising:
removing the support structure from the second side of the semiconductor wafer.
12 . The method of claim 1 , wherein a maximum height of the support structure in a cross-section of the support structure is larger than a thickness of the semiconductor wafer after reducing the thickness of the semiconductor wafer.
13 . The method of claim 1 , wherein a height of the support structure varies along a circumference of the support structure.
14 . A method for processing a semiconductor wafer, the method comprising:
reducing a thickness of the semiconductor wafer, wherein reducing the thickness of the semiconductor wafer comprises thinning the semiconductor wafer by at least one of grinding, laser ablation, etching the semiconductor wafer, and splitting the semiconductor wafer along a splitting region, wherein the splitting region is a buried splitting layer;
before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer;
after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side; and
removing a part of the semiconductor wafer so that a part of the buried splitting layer is uncovered.
15 . The method of claim 14 , wherein providing the buried splitting layer comprises:
forming the splitting region in the semiconductor wafer; and
forming an epitaxial semiconductor layer over the splitting region and/or over the semiconductor wafer.
16 . The method of claim 14 , wherein the part of the semiconductor wafer is removed starting at an outer edge of the semiconductor wafer.
17 . The method of claim 14 , wherein the support structure is attached to the second side of the semiconductor wafer by at least one of: gluing, bonding, adhesive bonding, laser melting, laser bonding, and soldering.
18 . The method of claim 14 , wherein the support structure is deposited at the second side of the semiconductor wafer with a three-dimensional (3D) printing process.
19 . The method of claim 14 , wherein the support structure comprises at least one of glass, sapphire, silicon, ceramic, carbon, plastic, and metal.
20 . The method of claim 14 , wherein a cross-sectional area of the support structure comprises an inner step, wherein the semiconductor wafer is located on the inner step after providing the support structure.
21 . The method of claim 14 , wherein an outer diameter of the support structure differs from a diameter of the semiconductor wafer by at most ±1% of the diameter of a semiconductor wafer.
22 . The method of claim 14 , wherein, in a cross-section, the support structure has a maximum height of at most 3 mm and at least 0.1 mm and/or a maximum width of at most 50 mm and at least 3 mm.
23 . The method of claim 14 , wherein a thickness of the semiconductor wafer is at most 300 μm after reducing the thickness of the semiconductor wafer.
24 . The method of claim 14 , further comprising:
forming at least a part of at least one electrical element structure on the semiconductor wafer; and/or
performing electrical testing of the at least one electrical element structure formed on the semiconductor wafer while the semiconductor wafer is mechanically supported by the support structure.
25 . The method of claim 14 , further comprising:
before reducing the thickness of the semiconductor wafer, forming an epitaxial semiconductor layer on the first side of the semiconductor wafer.
26 . The method of claim 14 , further comprising:
removing the support structure from the second side of the semiconductor wafer.
27 . The method of claim 14 , wherein a maximum height of the support structure in a cross-section of the support structure is larger than a thickness of the semiconductor wafer after reducing the thickness of the semiconductor wafer.
28 . The method of claim 14 , wherein a height of the support structure varies along a circumference of the support structure.