IP Library Granted Patent US 12713928
Granted Patent B2
US 12713928 · App. 17/833,580 · Granted Aug 18, 2026

EMI cage for microstrip routing via dual layer underfill concept

Inventors: Eng Huat Goh (Ayer Itam, MY); Jiun Hann Sir (Gelugor, MY); Chee Kheong Yoon (Bayan Lepas, MY); Telesphor Kamgaing (Chandler, AZ); Min Suet Lim (Gelugor, MY); Kavitha Nagarajan (Bangalore, IN); Chu Aun Lim (Hillsboro, OR)
Assignee: Intel Corporation
H10W42/20H10W44/20H10W70/685H10W44/216H10W44/248H10W70/65H10W72/01361H10W72/324H10W72/334H10W72/354H10W72/383H10W72/387H10W74/15H10W90/401H10W90/701H10W90/724H10W90/734
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Quick Facts
Patent No.
US 12713928
App. No.
17/833,580
Granted
Aug 18, 2026
Kind
B2
Abstract

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, a stiffener is around the die and over the package substrate. In an embodiment, an electrically non-conductive underfill is around first level interconnects (FLIs) between the package substrate and the die. In an embodiment, an electrically conductive layer is around the non-conductive underfill.

Claims (38)

1 . An electronic package, comprising:

a package substrate;

a die coupled to the package substrate;

a stiffener around the die and over the package substrate;

an electrically non-conductive underfill around first level interconnects (FLIs) between the package substrate and the die; and

an electrically conductive layer around the non-conductive underfill, wherein the non- conductive underfill is laterally intervening between the die and the electrically conductive layer such that the electrically conductive layer does not contact the die, and wherein the electrically conductive layer contacts the stiffener.

2 . The electronic package of claim 1 , further comprising:

a pad on the package substrate, and wherein the electrically conductive layer contacts the pad.

3 . The electronic package of claim 2 , wherein the pad is configured to be grounded.

4 . The electronic package of claim 1 , wherein a top surface of the electrically conductive layer is curved.

5 . The electronic package of claim 1 , wherein the electrically conductive layer is a conductive epoxy.

6 . The electronic package of claim 1 , wherein the electrically conductive layer is a conductive ink.

7 . The electronic package of claim 1 , wherein the package substrate comprises a core with a first four layers over the core and a second four layers under the core.

8 . The electronic package of claim 7 , wherein a topmost layer of the first four layers is a signal routing layer, and wherein a layer directly under the topmost layer is a ground layer.

9 . The electronic package of claim 8 , wherein the signal routing layer is a microstrip.

10 . The electronic package of claim 9 , wherein the electrically conductive layer electrically shields the microstrip.

11 . A method of forming an electronic package, comprising:

providing a die and a stiffener over a package substrate;

dispensing an underfill under the die around first level interconnects (FLIs);

dispensing an electrically conductive layer around the underfill; and

curing the electrically conductive layer, wherein the underfill is laterally intervening between the die and the electrically conductive layer such that the electrically conductive layer does not contact the die, and wherein the electrically conductive layer contacts the stiffener.

12 . The method of claim 11 , wherein the electrically conductive layer contacts a ground pad on the package substrate.

13 . The method of claim 11 , wherein the electrically conductive layer is a conductive epoxy.

14 . The method of claim 13 , wherein the conductive epoxy and the underfill are dispensed with the same nozzle.

15 . The method of claim 11 , wherein the electrically conductive layer is a conductive ink.

16 . The method of claim 11 , wherein the package substrate comprises a core and four layers above the core and four layers below the core.

17 . The method of claim 16 , wherein a microstrip routing is provided on a topmost layer of the package substrate.

18 . The method of claim 17 , wherein the electrically conductive layer electrically shields the microstrip routing.

19 . The method of claim 11 , wherein the curing results in a top surface of the electrically conductive layer being curved.

20 . An electronic system, comprising:

a board;

a package substrate coupled to the board;

a die coupled to the package substrate;

an underfill around first level interconnects (FLIs) between the die and the package substrate;

an electromagnetic interference (EMI) shield over the package substrate and around the underfill, wherein the underfill is laterally intervening between the die and the EMI shield such that the EMI shield does not contact the die; and

a stiffener on the package substrate and around the die, wherein the EMI shield contacts the stiffener.

21 . The electronic system of claim 20 , wherein the EMI shield includes a conductive epoxy or a conductive ink.

22 . The electronic system of claim 20 , wherein the EMI shield is configured to be grounded.