Energy harvest and storage device for semiconductor chips and methods for forming the same
A semiconductor structure may be located over a substrate, and may include a parallel connection of a first component and a second component. The first component includes a series connection of a diode and a capacitor that is selected from a metal-ferroelectric-metal capacitor and a metal-antiferroelectric-metal capacitor. The second component includes a battery structure. The semiconductor structure may be used as a combination of an energy harvesting device and an energy storage structure that utilizes heat from adjacent semiconductor devices or from other heat sources.
1 . A method of forming a semiconductor structure comprising an energy harvesting device and a battery structure within, or over, a substrate, the method comprising forming a layer stack on a substrate, wherein the layer stack includes, in a forward order or in a reverse order:
a first battery electrode layer;
an energy storage medium layer;
a second battery electrode layer,
a diode layer stack including a p-n junction or a p-i-n junction therein;
a first capacitor electrode layer;
a node dielectric layer that comprises a ferroelectric material layer or an antiferroelectric material layer; and
a second capacitor electrode layer.
2 . The method of claim 1 , further comprising:
forming semiconductor devices on the substrate; and
forming metal interconnect structures and dielectric material layers over the substrate, wherein the metal interconnect structures are electrically connected to the semiconductor devices, wherein the layer stack is formed over the dielectric material layers.
3 . The method of claim 2 , wherein:
a layer within the layer stack is formed as a planar material layer having a respective uniform thicknesses; and
the method comprises forming additional metal interconnect structures on the second battery electrode layer and on one of the second capacitor electrode layer and the first battery electrode layer.
4 . The method of claim 1 , further comprising forming a trench in an upper portion of the substrate, wherein the layer stack comprises a vertically-extending portion that is formed on a sidewall of the trench.
5 . The method of claim 1 , further comprising electrically connecting the first battery electrode layer and the second capacitor electrode layer by forming a metal interconnect structure that provides an electrically conductive path between the first battery electrode layer and the second capacitor electrode layer.
6 . A method of forming a semiconductor structure, comprising:
forming semiconductor devices on a semiconductor substrate;
forming first metal interconnect structures embedded in first dielectric material layers, wherein the first metal interconnect structures are electrically connected to the semiconductor devices;
forming a layer stack over the first dielectric material layers, wherein the layer stack includes, from bottom to top, a first battery electrode layer, an energy storage medium layer, a second battery electrode layer, a diode layer stack including a p-n junction or a p-i-n junction therein, a first capacitor electrode layer, a node dielectric layer that comprises a ferroelectric material layer or an antiferroelectric material layer, and a second capacitor electrode layer; and
electrically connecting the second capacitor electrode layer to the first battery electrode layer.
7 . The method of claim 6 , further comprising:
reducing lateral extents of the diode layer stack, the first capacitor electrode layer, the node dielectric layer, and the second capacitor electrode layer relative to a lateral extent of the second battery electrode layer; and
forming a second metal interconnect structure on a top surface segment of the second battery electrode layer.
8 . The method of claim 6 , further comprising:
forming second metal interconnect structures after formation of the layer stack, wherein an electrically conductive path that electrically connects the second capacitor electrode layer to the first battery electrode layer comprises a subset of the second metal interconnect structures;
forming a bonding-level dielectric material layer over the second metal interconnect structures; and
forming bonding structures through the bonding-level dielectric material layer on a respective one of the second metal interconnect structures.
9 . The method of claim 6 , wherein:
the first battery electrode layer is formed on a top surface of one of the first metal interconnect structures; and
an electrically conductive path that electrically connects the second capacitor electrode layer to the first battery electrode layer comprises a metal via structure that contacts a top surface segment of said one of the first metal interconnect structures.
10 . The method of claim 1 , further comprising forming a blocking dielectric layer between the first battery electrode layer and the energy storage medium layer, wherein the blocking dielectric layer comprises a dielectric metal oxide material and has a thickness in a range from 1 nm to 2 nm.
11 . The method of claim 1 , further comprising forming a conductive metal oxide layer between the first battery electrode layer and the energy storage medium layer, wherein the conductive metal oxide layer comprises a transition metal oxide and has a thickness in a range from 0.3 nm to 2.0 nm.
12 . The method of claim 1 , wherein the energy storage medium layer comprises an ionic crystal plate including an ionic crystal having ionic conductivity greater than 1.0×10 −5 S/cm in a temperature range from −40 degrees Celsius to 125 degrees Celsius, and wherein the energy storage medium layer has a thickness in a range from 30 nm to 1,000 nm.
13 . The method of claim 1 , wherein the diode layer stack comprises an n-doped semiconductor material layer and a p-doped semiconductor material layer, each having a thickness in a range from 10 nm to 100 nm.
14 . The method of claim 1 , wherein the node dielectric layer comprises:
a ferroelectric material selected from barium titanate, lead zirconate titanate, polyvinylidene fluoride, or aluminum nitride; or
an antiferroelectric material selected from lead zirconate or zirconium-doped hafnium oxide, and wherein the node dielectric layer has a thickness in a range from 4 nm to 100 nm.
15 . A method of forming a semiconductor structure within, or over, a substrate, the method comprising:
forming a layer stack including a combination of an energy harvesting device and a battery structure, wherein the layer stack includes, in a forward order or in a reverse order:
a first battery electrode layer;
an energy storage medium layer;
a second battery electrode layer,
a diode layer stack including a p-n junction or a p-i-n junction therein;
a first capacitor electrode layer;
a node dielectric layer that comprises a ferroelectric material layer or an antiferroelectric material layer; and
a second capacitor electrode layer,
wherein the method further comprises electrically connecting the second capacitor electrode layer to the first battery electrode layer.
16 . The method of claim 15 , further comprising:
forming semiconductor devices on the substrate; and
forming metal interconnect structures and dielectric material layers over the substrate, wherein the metal interconnect structures are electrically connected to the semiconductor devices, wherein the layer stack is formed over the dielectric material layers.
17 . The method of claim 16 , wherein:
a layer within the layer stack is formed as a planar material layer having a respective uniform thicknesses; and
the method comprises forming additional metal interconnect structures on the second battery electrode layer and on one of the second capacitor electrode layer and the first battery electrode layer.
18 . The method of claim 15 , further comprising forming a trench in an upper portion of the substrate, wherein the layer stack comprises a vertically-extending portion that is formed on a sidewall of the trench.
19 . The method of claim 15 , further comprising forming a metal interconnect structure that provides an electrically conductive path between the first battery electrode layer and the second capacitor electrode layer.
20 . The method of claim 15 , further comprising forming a blocking dielectric layer between the first battery electrode layer and the energy storage medium layer, wherein the blocking dielectric layer comprises a dielectric metal oxide material and has a thickness in a range from 1 nm to 2 nm.