Semiconductor devices comprising first to third overlay structures penetrating through first to third mold structures on overlay mark region and data storage systems including the same

1 . A semiconductor device, comprising:

a substrate having a first region and a second region;

a first stack structure including first gate electrodes stacked and spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate in the first region;

a first channel structure penetrating through the first stack structure and in contact with the substrate;

a second stack structure on the first stack structure and the first channel structure, the second stack structure including second gate electrodes stacked and spaced apart from each other in the vertical direction;

a second channel structure penetrating through the second stack structure and connected to the first channel structure;

a third stack structure on the second stack structure and the second channel structure, the third stack structure including third gate electrodes stacked and spaced apart from each other in the vertical direction;

a third channel structure penetrating through the third stack structure and connected to the second channel structure;

a first mold structure including first horizontal sacrificial layers stacked and spaced apart from each other in the vertical direction in the second region;

first overlay structures penetrating through at least a first portion of the first mold structure;

a second mold structure on the first mold structure and the first overlay structures, the second mold structure including second horizontal sacrificial layers stacked and spaced apart from each other in the vertical direction;

second overlay structures penetrating through at least a second portion of the second mold structure;

a third mold structure on the second mold structure and the second overlay structures, the third mold structure including third horizontal sacrificial layers stacked and spaced apart from each other in the vertical direction; and

third overlay structures penetrating through at least a third portion of the third mold structure,

wherein the first overlay structures, the second overlay structures, and the third overlay structures are in the first mold structure, the second mold structure and the third mold structure, respectively, and are on an overlay mark region, and

wherein, in the overlay mark region, the first overlay structures, the second overlay structures, and the third overlay structures are in at least one of quadrants defined by a first direction parallel to the upper surface of the substrate and a second direction parallel to the upper surface of the substrate and intersecting the first direction.

2 . The semiconductor device of claim 1 ,

wherein the first direction and the second direction are perpendicular to each other, and

wherein, in the at least one of the quadrants, the first overlay structures are parallel to each other, the second overlay structures are parallel to each other, and the third overlay structures are parallel to each other.

3 . The semiconductor device of claim 1 , wherein at least one of the first overlay structures, the second overlay structures, and the third overlay structures has a dot shape on a plan diagram.

4 . The semiconductor device of claim 1 ,

wherein, in a first quadrant among the quadrants, each of the first overlay structures, the second overlay structures, and the third overlay structures extends in the first direction, and

wherein, in a second quadrant adjacent to the first quadrant among the quadrants, each of the first overlay structures, the second overlay structures, and the third overlay structures extends in the second direction.

5 . The semiconductor device of claim 1 , wherein, in the at least one of the quadrants, the first overlay structures, the second overlay structures, and the third overlay structures are spaced apart from each other with a same distance therebetween.

6 . The semiconductor device of claim 1 , wherein, in the at least one of the quadrants, a first distance, which is a first minimum horizontal distance between the first overlay structures parallel to each other, is same as a second distance, which is a minimum horizontal distance between the second overlay structures parallel to each other, and a third distance, which is a second minimum horizontal distance between the third overlay structures parallel to each other.

7 . The semiconductor device of claim 1 , wherein, in the at least one of the quadrants, a first distance, which is a first minimum horizontal distance between the first overlay structures parallel to each other, is same as a second distance, which is a second minimum horizontal distance between the second overlay structures parallel to each other, and is greater than a third distance, which is a third minimum horizontal distance between the third overlay structures parallel to each other.

8 . The semiconductor device of claim 1 , wherein, in at least one of the quadrants, the first overlay structures, the second overlay structures, and the third overlay structures are alternately disposed.

9 . The semiconductor device of claim 1 ,

wherein, in the at least one of the quadrants, a fourth portion of each of the first overlay structures, the second overlay structures, and the third overlay structures extends in the first direction, and

wherein a fifth portion of each of the first overlay structures, the second overlay structures, and the third overlay structures extends in the second direction.

10 . The semiconductor device of claim 1 , wherein the first overlay structures, the second overlay structures, and the third overlay structures do not vertically overlap each other.

11 . The semiconductor device of claim 1 , wherein first upper surfaces of the first channel structure, the second channel structure and the third channel structure are coplanar with second upper surfaces of the first overlay structures, the second overlay structures, and the third overlay structures, respectively.

12 . The semiconductor device of claim 1 , wherein first upper surfaces of the first overlay structures are coplanar with first lower surfaces of the second overlay structures, and second upper surfaces of the second overlay structures are coplanar with second lower surfaces of the third overlay structures.

13 . The semiconductor device of claim 1 , wherein the first overlay structures, the second overlay structures, and the third overlay structures are spaced apart from each other when viewed in the vertical direction.

14 . A semiconductor device, comprising:

a substrate having a first region and a second region;

a first stack structure including first gate electrodes stacked and spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate in the first region;

a first channel structure penetrating through the first stack structure and in contact with the substrate;

a second stack structure on the first stack structure and the first channel structure, the second stack structure including second gate electrodes stacked and spaced apart from each other in the vertical direction;

a second channel structure penetrating through the second stack structure and connected to the first channel structure;

a third stack structure on the second stack structure and the second channel structure, the third stack structure including third gate electrodes stacked and spaced apart from each other in the vertical direction;

a third channel structure penetrating through the third stack structure and connected to the second channel structure;

a first mold structure including first horizontal sacrificial layers stacked and spaced apart from each other in the vertical direction in the second region;

first overlay structures penetrating through at least a first portion of the first mold structure;

a second mold structure on the first mold structure and the first overlay structures, the second mold structure including second horizontal sacrificial layers stacked and spaced apart from each other in the vertical direction;

second overlay structures penetrating through at least a second portion of the second mold structure;

a third mold structure on the second mold structure and the second overlay structures, the third mold structure including third horizontal sacrificial layers stacked and spaced apart from each other in the vertical direction; and

third overlay structures penetrating through at least a third portion of the third mold structure,

wherein the first overlay structures, the second overlay structures, and the third overlay structures are in the first mold structure, the second mold structure, and the third mold structure, respectively, and are on an overlay mark region, and are in at least one quadrant with respect to a central point of the overlay mark region,

wherein a fourth portion of the first overlay structures extends in a first direction parallel to the upper surface of the substrate, and a fifth portion of the first overlay structures extends in second direction perpendicular to the vertical direction,

wherein a sixth portion of the second overlay structures extends in the first direction, and a seventh portion of the second overlay structures extends in the second direction, and

wherein an eighth portion of the third overlay structures extends in the first direction, and a ninth portion of the third overlay structures extends in the second direction.

15 . The semiconductor device of claim 14 , wherein a cross-sectional surface of at least one of the first overlay structures, the second overlay structures, and the third overlay structures taken in the first direction and the second direction has a dot shape.

16 . The semiconductor device of claim 14 , wherein, in the at least one quadrant, a first distance, which is a first minimum horizontal distance between the first overlay structures parallel to each other, is same as a second distance, which is a second minimum horizontal distance between the second overlay structures parallel to each other, and a third distance, which is a third minimum horizontal distance between the third overlay structures parallel to each other.

17 . The semiconductor device of claim 14 , wherein, in the at least one quadrant, the first overlay structures, the second overlay structures, and the third overlay structures are alternately disposed.

18 . The semiconductor device of claim 14 , wherein a number of the first overlay structures, a first number of the second overlay structures and a second number of the third overlay structures are same.

19 . A data storage system, comprising:

a semiconductor storage device including a substrate having a first region and a second region, circuit devices on one side of the substrate, and input/output pad electrically connected to the circuit devices; and

a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device,

wherein the semiconductor storage device includes,

a first stack structure including first gate electrodes stacked and spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate in the first region,

a first channel structure penetrating through the first stack structure and in contact with the substrate,

a second stack structure on the first stack structure and the first channel structure, the second stack structure including second gate electrodes stacked and spaced apart from each other in the vertical direction,

a second channel structure penetrating through the second stack structure and connected to the first channel structure,

a third stack structure on the second stack structure and the second channel structure, the third stack structure including third gate electrodes stacked and spaced apart from each other in the vertical direction,

a third channel structure penetrating through the third stack structure and connected to the second channel structure,

a first mold structure including first horizontal sacrificial layers stacked and spaced apart from each other in the vertical direction in the second region,

first overlay structures penetrating through at least a first portion of the first mold structure,

a second mold structure on the first mold structure and the first overlay structures, the second mold structure including second horizontal sacrificial layers stacked and spaced apart from each other in the vertical direction,

second overlay structures penetrating through at least a second portion of the second mold structure,

a third mold structure on the second mold structure and the second overlay structures, the third mold structure including third horizontal sacrificial layers stacked and spaced apart from each other in the vertical direction, and

third overlay structures penetrating through at least a third portion of the third mold structure,

wherein the first overlay structures, the second overlay structures, and the third overlay structures are in the first mold structure, the second mold structure, and the third mold structure, respectively, and

wherein the first overlay structures, the second overlay structures, and the third overlay structures are in at least one of quadrants defined by a first direction parallel to the upper surface of the substrate and a second direction parallel to the upper surface of the substrate and intersecting the first direction.

20 . The data storage system of claim 19 ,

wherein a fourth portion of the first overlay structures extends in the first direction, and a fifth portion of the first overlay structures extends in the second direction,

wherein a sixth portion of the second overlay structures extends in the first direction, and a seventh portion of the second overlay structures extends in the second direction, and

wherein an eighth portion of the third overlay structures extends in the first direction, and a ninth portion of the third overlay structures extends in the second direction.