IP Library Granted Patent US 12,713,936
Granted Patent B1
US 12,713,936 · App. 18/114,188 · Granted Aug 18, 2026

Cross-mesh power distribution layout with low loop inductance and method of manufacture

Inventors: Nathaniel Unger (San Jose, CA); Yiqi Tang (Allen, TX)
Assignee: Astera Labs, Inc.
H10W70/05H10W70/65H10W70/685H10W90/724
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Quick Facts
Patent No.
US 12,713,936
App. No.
18/114,188
Filed
Feb 24, 2023
Granted
Aug 18, 2026
Kind
B1
Art Unit
2817
USPC
257/737
Abstract

An electronic system having a mounting substrate with a plurality of mesh layers arranged in alternating order with adjacent power strips and ground strips. The opposite current flow within the alternating strips improves the loop inductance and can result in a low package loop inductance and low parasitic resistance. Increasing mutual inductance by controlling the direction of the current flow can reduce total loop inductance. The electronic components including ball grid array devices in a flip chip configuration can be attached to the mounting substrate to increase performance. The use of a plurality of the mesh layers can improve degassing performance due to the mesh structure, reduce the copper imbalance and help reduce potential warpage of the package.

Claims (16)

1 . A method of manufacture of an electronic system comprising:

forming a printed circuit board having a plurality of layers, the printed circuit board having a bottom layer and a top layer, the top layer having contact bumps exposed on the top side for attaching to an electronic component;

forming a first mesh layer over the bottom layer, the first mesh layer having a plurality of power strips and a plurality of ground strips arranged in parallel with a long axis of the power strips of the first mesh layer; and

forming a second mesh layer over the first mesh layer, the second mesh layer having a plurality of power strips and ground strips arranged in parallel with a long axis of the power strips of the second mesh layer, and the second mesh layer at a mesh angle to the first mesh layer and wherein each of the power strips and the ground strips alternating with one another, the power strips and ground strips having current flows in opposite directions for reducing a loop inductance.

2 . The method as claimed in claim 1 , further comprising attaching an electronic component to the contact bumps on the top side of the printed circuit board.

3 . The method as claimed in claim 1 , wherein forming the second mesh layer includes forming second mesh layer having an even strip configuration with a second strip configured as a power strip.

4 . The method as claimed in claim 1 , wherein forming the second mesh layer includes forming second mesh layer having a mesh angle larger than 0 degrees but less than 180 degrees.

5 . The method as claimed in claim 1 , wherein forming the first mesh layer includes forming the first mesh layer having one of the power strips with a strip protrusion extending toward a protrusion gap of one of the ground strips and the strip protrusion electrically coupled to the second mesh layer with a conductive via.

6 . An electronic system comprising:

a mounting substrate having a plurality of layers, the mounting substrate having a bottom layer and a top layer; and wherein:

the mounting substrate having a first mesh layer over the bottom layer, the first mesh layer having a plurality of power strips and a plurality of ground strips arranged in parallel with a long axis of the power strips of the first mesh layer, and the mounting substrate is a printed circuit board and the top layer having contact bumps exposed on the top side for attaching to an electronic component, and

the mounting substrate having a second mesh layer over the first mesh layer, the second mesh layer having a plurality of power strips and ground strips arranged in parallel with a long axis of the power strips of the second mesh layer, and the second mesh layer at a mesh angle to the first mesh layer, and wherein each of the power strips and the ground strips alternating with one another, the power strips and ground strips having current flows in opposite directions for reducing a loop inductance.

7 . The system as claimed in claim 6 , further comprising an electronic component attached to the contact bumps on the top side of the printed circuit board.

8 . The system as claimed in claim 6 , wherein the second mesh layer having an even strip configuration with a second strip configured as a power strip.

9 . The system as claimed in claim 6 , wherein the second mesh layer having the mesh angle larger than 0 degrees but less than 180 degrees.

10 . The system as claimed in claim 6 , wherein one of the power strips having a strip protrusion extending toward a protrusion gap of one of the ground strips and the strip protrusion electrically coupled to the second mesh layer with a conductive via.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2023
From: UNGER, NATHANIEL; TANG, YIQI
To: ASTERA LABS, INC.
Reel/Frame 063448/0799 →
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