QFN package comprising two electronic chips with different substrates
A package includes a mounting plate having a first part able to dissipate heat and a second part able to transmit and/or receive electrical signals. A cladding houses a first electronic chip and second electronic chip. The first electronic chip has a first semiconductor substrate (giving off, in operation, a first quantity of heat) mounted to the first part of the mounting plate and electrically connected by wires to the second part of the mounting plate. The second electronic chip has a second semiconductor substrate (giving off, in operation, a second quantity of heat) mounted to an interposer support including an interconnection network. An array of connection balls interconnects the interposer support to the first part of the mounting plate and the second part of the mounting plate. The first and second semiconductor substrates are different.
1 . A package, comprising:
a leadframe having a die pad part configured to dissipate heat, a first set of leads part, and a second set of leads part configured to transmit and/or receive electrical signals;
a first electronic chip having a first semiconductor substrate;
a second electronic chip having a second semiconductor substrate;
wherein the first and second semiconductor substrates are different;
a laminated interconnection support having a mounting face and an attaching face opposite to the mounting face;
a cladding encapsulating the first and second electronic chips and the laminated interconnection support;
wherein the first electronic chip is mounted to the die pad part of the leadframe, electrically coupled to the second electronic chip by connecting wires, and electrically coupled to the second set of leads part of the leadframe by connecting wires; and
wherein the second electronic chip is mounted to the mounting face of the laminated interconnection support, with the attaching face of the laminated interconnection support mounted to the die pad part of the leadframe through a first array of connection balls, and with the attaching face of the laminated interconnection support electrically coupled to the first set of leads part of the leadframe by said a first array of connection balls.
2 . The package according to claim 1 , wherein the first semiconductor substrate is configured to give off, in operation, a first quantity of heat, wherein the second semiconductor substrate is configured to give off, in operation, a second quantity of heat, and wherein the second quantity of heat is less than the first quantity of heat.
3 . The package according to claim 2 , wherein the first quantity of heat corresponds to a dissipated power of several watts.
4 . The package according to claim 3 , wherein the second quantity of heat corresponds to a dissipated power of less than 1 watt.
5 . The package according to claim 1 , being of the flat no-leads type.
6 . The package according to claim 1 , wherein the first semiconductor substrate includes gallium nitride.
7 . The package according to claim 6 , wherein the second semiconductor substrate includes silicon.
8 . The package according to claim 1 , wherein the mounting face of the laminated interconnection support is connected to the second electronic chip by a second array of connection balls, and wherein the laminated interconnection support comprises an interconnection network configured to electrically couple the first array of connection balls and the second array of connection balls.
9 . The package according to claim 8 , wherein the connecting wires include first connecting wires and second connecting wires, the first electronic chip has a rear face attached to the part of the leadframe by a layer of thermally conductive glue and a front face electrically connected to the part of the leadframe by the first connecting wires and electrically connected to the interconnection network by the second connecting wires.
10 . The package according to claim 8 , further comprising at least one surface-mount device component mounted to the laminated interconnection support and encapsulated within the cladding, and wherein the interconnection network of the laminated interconnection support is also configured to electrically couple said at least one surface-mount device component to the first electronic chip and to the second electronic chip.
11 . A package, comprising:
a leadframe including a die pad and a plurality of leads;
a first electronic chip having a first semiconductor substrate with a rear face mounted to the die pad and a front face electrically connected to first ones of the plurality of leads by first bonding wires;
a support including an interconnection network with a rear face electrically connected by first bumps to the die pad and to second ones of the plurality of leads;
a second electronic chip having a second semiconductor substrate with a first face mounted to a front face of the support and electrically connected to the interconnection network; and
a cladding encapsulating the leadframe, the support and the first and second electronic chips;
wherein the first and second semiconductor substrates are different.
12 . The package of claim 11 , wherein the first face of the second electronic chip is a front face with second bumps electrically connected to the interconnection network at the front face of the support.
13 . The package of claim 11 , further comprising second bonding wires electrically connecting the front face of the first electronic chip to the interconnection network at the front face of the support.
14 . The package of claim 11 , further comprising a surface mount device mounted and electrically connected to the interconnection network at the front face of the support, wherein the surface mount device is encapsulated within the cladding.