Transistor package and process of implementing the transistor package

1 . A package comprising:

at least one semiconductor device;

a package support configured to support the at least one semiconductor device;

a silicon carbide (SiC) integrated passive device (IPD); and

electrical connection portions comprising at least one of the following: electrical connection portions extending from the package support, electrical connection portions configured as a bond wire device connection, electrical connection portions configured as a bump ball connection, and/or electrical connection portions configured as a stud bump connection,

wherein the electrical connection portions connect between the at least one semiconductor device and the package support; and

wherein the silicon carbide (SiC) integrated passive device (IPD) is between the package support and the at least one semiconductor device.

2 . The package according to claim 1 further comprising a heat sink on the at least one semiconductor device,

wherein the at least one semiconductor device is configured as a flip chip.

3 . The package according to claim 1 wherein the electrical connection portions extend from the package support; and wherein the electrical connection portions comprise a solder connection arranged on a tip thereof.

4 . The package according to claim 3 wherein the solder connection is configured with a plated solder portion; and wherein the electrical connection portions are further between the at least one semiconductor device and the silicon carbide (SiC) integrated passive device (IPD).

5 . The package according to claim 3 wherein the solder connection is configured with solder printing; and wherein the electrical connection portions are further between the at least one semiconductor device and the silicon carbide (SiC) integrated passive device (IPD).

6 . The package according to claim 3 wherein the solder connection is configured with solder arranged to implement a solder reflow; and wherein the electrical connection portions are further between the at least one semiconductor device and the silicon carbide (SiC) integrated passive device (IPD).

7 . The package according to claim 1 further comprising a heat sink on the at least one semiconductor device, wherein the at least one semiconductor device comprises a gallium nitride (GaN) silicon carbide (SiC) transistor.

8 . The package according to claim 1 wherein the package support comprises a printed circuit board (PCB), a printed wiring board (PWB), and/or a printed circuit board assembly (PCBA); wherein the electrical connection portions extend from the package support; and wherein the electrical connection portions are further between the at least one semiconductor device and the silicon carbide (SiC) integrated passive device (IPD).

9 . The package according to claim 1 wherein the electrical connection portions comprise a vertical portion that extends through the package support.

10 . The package according to claim 1 wherein the electrical connection portions comprise a vertical portion implemented by a plated-through hole that extends through the package support.

11 . The package according to claim 1 wherein the electrical connection portions comprise an etched portion of the package support.

12 . The package according to claim 1 wherein the electrical connection portions are configured as a bond wire device connection connected to a bond pad on the package support.

13 . The package according to claim 12 wherein the bond wire device connection comprises a solder connection arranged on a tip thereof.

14 . The package according to claim 1 wherein the electrical connection portions extend from the package support: wherein the electrical connection portions comprise the bump ball connection; and wherein the electrical connection portions are further between the at least one semiconductor device and the silicon carbide (SiC) integrated passive device (IPD).

15 . The package according to claim 14 wherein the bump ball connection is configured with a plurality of metallic bump balls.

16 . The package according to claim 14 wherein the bump ball connection comprises a solder connection arranged on a top surface thereof.

17 . The package according to claim 1 wherein the electrical connection portions extend from the package support; wherein the electrical connection portions are further between the at least one semiconductor device and the silicon carbide (SiC) integrated passive device (IPD); and wherein the electrical connection portions comprise the stud bump connection.

18 . The package according to claim 17 wherein the stud bump connection is arranged on electrical contact pads of the at least one semiconductor device and on bond pads of the package support.

19 . The package according to claim 1 further comprising:

a heat sink; and

an over-mold configured to at least partially surround the at least one semiconductor device.

20 . The package according to claim 1 further comprising a heat sink,

wherein the electrical connection portions are further arranged between the at least one semiconductor device and the silicon carbide (SiC) integrated passive device (IPD).

21 . The package according to claim 1 further

wherein the electrical connection portions are further arranged between the at least one semiconductor device and other components.

22 . The package according to claim 1 wherein the electrical connection portions are further arranged between the package support and other components.

23 . The package according to claim 1 wherein the electrical connection portions are further arranged between the at least one semiconductor device and other components.

24 . A package comprising:

at least one semiconductor device;

a package support configured to support the at least one semiconductor device;

a silicon carbide (SiC) integrated passive device (IPD);

a heat sink on the at least one semiconductor device; and

electrical connection portions configured and/or operable to connect between the at least one semiconductor device and the package support; and

wherein the electrical connection portions connect between the at least one semiconductor device and the package support; and

wherein the silicon carbide (SiC) integrated passive device (IPD) is between the package support and the at least one semiconductor device.

25 . The package according to claim 24

wherein the at least one semiconductor device is configured as a flip chip; and

wherein the electrical connection portions are further between the at least one semiconductor device and the silicon carbide (SiC) integrated passive device (IPD).

26 . The package according to claim 24 further comprising an over-mold configured to at least partially surround the at least one semiconductor device.

27 . A package comprising:

at least one semiconductor device;

a package support configured to support the at least one semiconductor device;

a silicon carbide (SiC) integrated passive device (IPD);

a heat sink on the at least one semiconductor device; and

electrical connection portions configured and/or operable to connect between the at least one semiconductor device and the package support;

wherein the electrical connection portions are between the at least one semiconductor device and the silicon carbide (SiC) integrated passive device (IPD); and

wherein the silicon carbide (SiC) integrated passive device (IPD) is between the package support and the at least one semiconductor device.

28 . The package according to claim 27 wherein the at least one semiconductor device is configured as a flip chip; and wherein the electrical connection portions further connect between the at least one semiconductor device and the package support.

29 . The package according to claim 27 further comprising an over-mold configured to at least partially surround the at least one semiconductor device.