IP Library › Granted Patent US 12713949
Granted Patent B2
US 12713949 · App. 18/123,154 · Granted Aug 18, 2026

Semiconductor device and method for manufacturing the same

Inventors: Hung-Wei Tsai (Hsinchu, TW); Chih-Wei Wu (Hsinchu, TW); Ying-Ching Shih (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10W70/635H10W90/00H10W72/07227H10W72/07236H10W72/07253H10W72/237H10W74/00H10W90/721H10W90/722
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Quick Facts
Patent No.
US 12713949
App. No.
18/123,154
Granted
Aug 18, 2026
Kind
B2
Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a first semiconductor module, a reorientation layer, a second semiconductor module and a plurality of jointing materials. The first semiconductor module has at least one first conductive structure and at least one second conductive structure. The reorientation layer covers part of the second conductive structure to form an opening. The second semiconductor module has at least one third conductive structure and at least one fourth conductive structure. The jointing materials are disposed between the first conductive structure and the third conductive structure, and disposed in the opening.

Claims (36)

1 . A method for manufacturing a semiconductor device, comprising:

forming a first semiconductor module, including at least one first conductive structure and at least one second conductive structure;

forming a reorientation layer, covering part of the second conductive structure to form an opening; and

placing a second semiconductor module including at least one third conductive structure and at least one fourth conductive structure on the first semiconductor module, wherein the third conductive structure is substantially aligned with the first conductive structure, and the fourth conductive structure is offset from the second conductive structure;

wherein a material of the reorientation layer is a dielectric material.

2 . The method according to claim 1 , further comprising:

forming a plurality of jointing materials on the first conductive structure and in the opening; and

reflowing the jointing materials to join the first conductive structure and the third conductive structure and join the second conductive structure and the fourth conductive structure.

3 . The method for manufacturing the semiconductor device according to claim 2 , wherein the first conductive structure is disposed on an element, the element and the second conductive structure are formed individually, and the third conductive structure and the fourth conductive structure are disposed on a single element.

4 . The method for manufacturing the semiconductor device according to claim 2 , wherein the first conductive structure is a bump disposed on a first chip, the second conductive structure is a through mold via (TMV), the second conductive structure and the first chip are formed individually, and the third conductive structure and the fourth conductive structure are bumps disposed on a second chip.

5 . The method for manufacturing the semiconductor device according to claim 2 , wherein in a top view of the semiconductor device, a center of the opening and a center of the second conductive structure are located at different locations.

6 . The method for manufacturing the semiconductor device according to claim 2 , wherein in a top view of the semiconductor device, a center of the fourth conductive structure is substantially overlapped with a center of the opening.

7 . The method for manufacturing the semiconductor device according to claim 2 , wherein a thickness of each of the jointing materials is substantially identical to a thickness of the reorientation layer.

8 . The method for manufacturing the semiconductor device according to claim 2 , wherein the second conductive structure is larger than the first conductive structure.

9 . The method for manufacturing the semiconductor device according to claim 2 , wherein the fourth conductive structure is larger than the third conductive structure.

10 . A method for manufacturing a semiconductor device, comprising:

forming a first semiconductor module, including at least one first conductive structure and at least one second conductive structure, wherein in a top view of the semiconductor device, the second conductive structure is larger than the at least one first conductive structure;

forming a reorientation layer, covering part of the second conductive structure to form an opening; and

placing a second semiconductor module including at least one third conductive structure and at least one fourth conductive structure on the first semiconductor module, wherein the third conductive structure is substantially aligned with the first conductive structure, and the fourth conductive structure is offset from the second conductive structure;

wherein in a top view of the semiconductor device, a center of the opening and a center of the second conductive structure are located at different locations.

11 . The method according to claim 10 , further comprising:

forming a plurality of jointing materials on the first conductive structure and in the opening; and

reflowing the jointing materials to join the first conductive structure and the third conductive structure and join the second conductive structure and the fourth conductive structure.

12 . The method for manufacturing the semiconductor device according to claim 11 , wherein the first conductive structure is disposed on an element, the element and the second conductive structure are formed individually, and the third conductive structure and the fourth conductive structure are disposed on a single element.

13 . The method for manufacturing the semiconductor device according to claim 11 , wherein the first conductive structure is a bump disposed on a first chip, the second conductive structure is a through mold via (TMV), the second conductive structure and the first chip are formed individually, and the third conductive structure and the fourth conductive structure are bumps disposed on a second chip.

14 . The method for manufacturing the semiconductor device according to claim 11 , wherein in a top view of the semiconductor device, a center of the fourth conductive structure is substantially overlapped with a center of the opening.

15 . The method for manufacturing the semiconductor device according to claim 11 , wherein a material of the reorientation layer is a dielectric material.

16 . The method for manufacturing the semiconductor device according to claim 11 , wherein a thickness of each of the jointing materials is substantially identical to a thickness of the reorientation layer.

17 . The method for manufacturing the semiconductor device according to claim 11 , wherein the second conductive structure is larger than the first conductive structure.

18 . A method for manufacturing a semiconductor device, comprising:

forming a first semiconductor module, including at least one first conductive structure and at least one second conductive structure, wherein in a top view of the semiconductor device, sizes of the second conductive structure and the at least one first conductive structure are different;

forming a reorientation layer, covering part of the second conductive structure to form an opening; and

placing a second semiconductor module including at least one third conductive structure and at least one fourth conductive structure on the first semiconductor module, wherein the third conductive structure is substantially aligned with the first conductive structure, and the fourth conductive structure is offset from the second conductive structure;

wherein the first conductive structure is a bump disposed on a first chip, the second conductive structure is a through mold via (TMV), the second conductive structure and the first chip are formed individually, and the third conductive structure and the fourth conductive structure are bumps disposed on a second chip.

19 . The method for manufacturing the semiconductor device according to claim 18 , wherein in a top view of the semiconductor device, a center of the opening and a center of the second conductive structure are located at different locations.

20 . The method for manufacturing the semiconductor device according to claim 18 , wherein in a top view of the semiconductor device, a center of the fourth conductive structure is substantially overlapped with a center of the opening.