IP Library › Granted Patent US 12713950
Granted Patent B2
US 12713950 · App. 17/939,824 · Granted Aug 18, 2026

Three-dimensional integration of dies in an integrated circuit device

Inventors: Jeremy D. Ecton (Gilbert, AZ); Brandon Christian Marin (Gilbert, AZ); Srinivas V. Pietambaram (Chandler, AZ); Gang Duan (Chandler, AZ); Suddhasattwa Nad (Chandler, AZ)
Assignee: Intel Corporation
H10W70/65H10W70/611H10W70/685H10W74/117H10W90/00H10W90/794
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Quick Facts
Patent No.
US 12713950
App. No.
17/939,824
Granted
Aug 18, 2026
Kind
B2
Abstract

In one embodiment, an integrated circuit device includes a first layer having input/output (IO) hub circuitry to interconnect a plurality of integrated circuit dies, and a second layer having a plurality of integrated circuit dies electrically connected to the IO hub circuitry. The first layer may include glass, and the IO hub circuitry may be in a die embedded within the first layer. The integrated circuit dies may be electrically connected to the IO hub circuitry through an interposer.

Claims (35)

1 . An integrated circuit device comprising:

a package substrate; and

an integrated circuit device coupled to the package substrate, the integrated circuit device comprising:

a first layer comprising glass and an input/output (IO) hub circuitry die embedded in a cavity of the glass, the IO hub circuitry die to interconnect a plurality of integrated circuit dies, the IO hub circuitry die electrically connected to the package substrate; and

a second layer on the first layer, the second layer comprising a plurality of integrated circuit dies, wherein at least two of the integrated circuit dies are electrically connected to the IO hub circuitry die through an interposer in the second layer, the interposer comprising circuitry to interconnect the at least two integrated circuit dies.

2 . The integrated circuit device of claim 1 , wherein the first layer comprises conductive pillars electrically coupling a top side of the first layer to the package substrate, at least one of the integrated circuit dies electrically connected to the conductive pillars.

3 . The integrated circuit device of claim 1 , wherein at least one integrated circuit die is directly connected to the IO hub circuitry die.

4 . The integrated circuit device of claim 1 , wherein at least one integrated circuit die is connected to the IO hub circuitry die through solder bonds.

5 . The integrated circuit device of claim 1 , wherein the interposer is directly connected to the IO hub circuitry die.

6 . The integrated circuit device of claim 1 , wherein the interposer is connected to the IO hub circuitry die through solder bonds.

7 . The integrated circuit device of claim 1 , wherein the second layer comprises a mold material around the plurality of integrated circuit dies.

8 . The integrated circuit device of claim 1 , wherein the first layer comprises a mold material around the IO hub circuitry die.

9 . A system comprising:

a main circuit board; and

an integrated circuit package coupled to the main circuit board, the integrated circuit package comprising:

a package substrate; and

an integrated circuit device connected to the package substrate, the integrated circuit device comprising:

a first integrated circuit die embedded in a first layer comprising glass, the first integrated circuit die electrically connected to the package substrate; and

a plurality of second integrated circuit dies in a second layer, the second integrated circuit dies electrically connected to the first integrated circuit die, wherein at least two second integrated circuit dies are connected to the first integrated circuit die through an interposer, the interposer comprising circuitry to interconnect the at least two second integrated circuit dies.

10 . The system of claim 9 , wherein the first integrated circuit die comprises input/output (IO) hub circuitry.

11 . The system of claim 9 , wherein at least one of the second integrated circuit dies is directly connected to the first integrated circuit die.

12 . The system of claim 9 , wherein at least one of the second integrated circuit dies is connected to the first integrated circuit die through a solder bond.

13 . The system of claim 9 , wherein the interposer is directly connected to the first integrated circuit die.

14 . The system of claim 9 , wherein the interposer is connected to the first integrated circuit die through solder bonds.

15 . The system of claim 9 , wherein the second layer comprises a mold material around the second integrated circuit dies.

16 . The system of claim 9 , wherein the first integrated circuit die is electrically connected to the package substrate through solder bonds.

17 . A method of manufacturing an integrated circuit package, comprising:

forming an integrated circuit chip, comprising:

embedding a first integrated circuit die within a cavity of a glass layer;

attaching an assembly comprising a plurality of second integrated circuit dies and an interposer to a top side of the glass layer, wherein attaching the assembly directly couples the interposer to the first integrated circuit die; and

depositing a mold material around the assembly; and

coupling the integrated circuit chip to a package substrate.

18 . The method of claim 17 , wherein attaching the assembly comprises coupling the interposer to the first integrated circuit die using a hybrid bonding technique.

19 . The method of claim 18 , wherein the hybrid bonding technique is a polyimide-based hybrid bonding technique.

20 . The method of claim 18 , wherein the hybrid bonding technique is a silicon oxide-based hybrid bonding technique.