Integrated circuit package
An integrated circuit package includes a support substrate and a cover fastened on a first face of the support substrate. The cover and support substrate define a housing containing an electronic integrated circuit chip having a first face equipped with electrically conductive protruding elements. A first space between the cover and a second face of the electronic integrated circuit chip is filled with a first shape memory material in the austenitic state. A second space between each pair of electrically conductive protruding elements and electrically conductive contact pads of the support substrate is filled with a second shape memory material in the austenitic state.
1 . An integrated circuit package, comprising:
a support substrate including a first face with electrically conductive contact pads and an insulating layer over the first face of the support substrate and including an opening extending through the insulating layer at each electrically conductive contact pad;
a cover fastened on a first face of the support substrate and defining, with the support substrate, a housing;
at least one electronic integrated circuit chip contained within the housing;
wherein the at least one electronic integrated circuit chip has a first face equipped with electrically conductive protruding elements and a second face opposite to the first face; and
a layer of a first shape memory material located within each opening of the insulating layer and in contact with the electrically conductive contact pad;
wherein each electrically conductive protruding element of the at least one electronic integrated circuit chip extends into the opening of the insulating layer to make contact with the layer of the first shape memory material; and
wherein the electrically conductive protruding elements are in electrical cooperation with the electrically conductive contact pads of the support substrate via the layers of the first shape memory material.
2 . The package according to claim 1 , wherein the first shape memory material is thermally conductive.
3 . The package according to claim 1 , wherein a space between the first face of the at least one electronic integrated circuit chip and the first face of the support substrate is devoid of filler material.
4 . The package according to claim 1 , wherein a space between the first face of the at least one electronic integrated circuit chip and the first face of the support substrate is devoid of adhesive material.
5 . The package according to claim 1 , wherein the first shape memory material has a temperature of end of transition to an austenitic state comprised between 40° C. and 100° C.
6 . The package according to claim 1 , wherein the first shape memory material contains a nickel-titanium alloy.
7 . The package according to claim 6 , wherein the first shape memory material contains a first amount of non-porous nickel-titanium alloy and a second amount of porous nickel-titanium alloy.
8 . The package according to claim 7 , wherein the second amount is less than or equal to 10% of the total amount of nickel-titanium alloy.
9 . The package according to claim 7 , wherein the porous nickel-titanium alloy has a modulus of elasticity comprised between 10 GPa and 100 GPa.
10 . The package according to claim 6 , wherein the first shape memory material contains copper in an amount which is less than or equal to 5% of a total amount of the first shape memory material.
11 . The package according to claim 1 , wherein a space between the second face of the at least one electronic integrated circuit chip and the cover is filled with a second shape memory material.
12 . The package according to claim 11 , wherein the second shape memory material is thermally conductive.
13 . The package according to claim 12 , wherein the first shape memory material and the second shape memory material are identical.
14 . The package according to claim 11 , wherein the first shape memory material and the second shape memory material each contain a nickel-titanium alloy.
15 . The package according to claim 14 , wherein the first shape memory material and the second shape memory material each contain a first amount of non-porous nickel-titanium alloy and a second amount of porous nickel-titanium alloy.
16 . The package according to claim 15 , wherein the second amount is less than or equal to 10% of the total amount of nickel-titanium alloy.
17 . The package according to claim 15 , wherein the porous nickel-titanium alloy has a modulus of elasticity comprised between 10 GPa and 100 GPa.
18 . The package according to claim 11 , wherein the first shape memory material and the second shape memory material each also contain copper in an amount which is less than or equal to 5% of a total amount of the corresponding shape memory material.
19 . A method for manufacturing an integrated circuit package, comprising:
a) providing at least one electronic integrated circuit chip having a first face equipped with electrically conductive protruding elements;
b) providing a support substrate having a first face equipped with electrically conductive contact pads and an insulating layer over the first face of the support substrate and including an opening extending through the insulating layer at each electrically conductive contact pad;
c) providing within each opening of the insulating layer and in contact with the electrically conductive contact pad a first layer of a first shape memory material in a martensitic state and having an initial thickness;
d) deforming the first layer so as to give it a second thickness which is less than the initial thickness and depositing the first layer thus deformed on the electrically conductive contact pads;
e) flipping the at least one electronic integrated circuit chip and causing the protruding elements to extend into the openings of the insulating layer to make contact with the first layer of the first shape memory material;
f) fastening a cover on the first face of the support substrate; and
g) heating the structure obtained in step f) to a temperature which is higher than a temperature of end of transition to an austenitic state of the first shape memory material so that the first layer expands in thickness to apply a pressure against on the electrically conductive protruding elements.
20 . The method according to claim 19 , wherein the first shape memory material contains a nickel-titanium alloy.
21 . The method according to claim 19 , further comprising:
providing a second layer of a second shape memory material in a martensitic state and having an initial thickness;
deforming the second layer so as to give it a second thickness which is less than the initial thickness and depositing the second layer thus deformed on a second face of the at least one electronic integrated circuit chip which is opposite to the first face;
wherein step f) fastens the cover over the second layer, leaving a space between the second layer and the cover; and
wherein the temperature of the heating in step g) is higher than a temperature of end of transition to an austenitic state of the second shape memory material so that the second layer expands in thickness to fill said space by ensuring a pressure on the cover.