IP Library Granted Patent US 12,713,970
Granted Patent B2
US 12,713,970 · App. 18/472,309 · Granted Aug 18, 2026

Semiconductor device

Inventors: Yoichi Sasaki (Kariya-city, JP); Satoru Wakiyama (Kariya-city, JP)
Assignee: DENSO CORPORATION
H10W74/131H10W70/09H10W70/60H10W70/6528
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Quick Facts
Patent No.
US 12,713,970
App. No.
18/472,309
Granted
Aug 18, 2026
Kind
B2
Abstract

A semiconductor device includes: a die; a mold material layer in which the die is embedded in a state where an electrode surface of the die is exposed from a surface of the mold material layer; and a redistribution layer provided on a surface of the mold material layer and having an insulating layer and a wiring in a multilayer state, as a fan out wafer level package. The semiconductor device further has a reinforcing structure made of a material harder than the insulating layer, on the insulating layer of the redistribution layer. The reinforcing structure is located between the wiring and a surface of the mold material layer. The reinforcing structure is at a position corresponding to a boundary region between the die and the mold material layer.

Claims (14)

1 . A semiconductor device comprising:

a die;

a mold material layer in which the die is embedded in a state where an electrode surface of the die is exposed from a surface of the mold material layer; and

a redistribution layer provided on a surface of the mold material layer and having an insulating layer and a wiring in a multilayer state, as a fan out wafer level package, wherein

the semiconductor device further has a reinforcing structure made of a material harder than the insulating layer, on the insulating layer of the redistribution layer,

the reinforcing structure is located between the wiring and a surface of the mold material layer, and

the reinforcing structure is positioned to be aligned with a boundary line, wherein the boundary line is between the die and the mold material layer, wherein the reinforcing structure is formed by partially increasing a thickness of the wiring, wherein

the redistribution layer includes a ground plane for noise suppression,

the reinforcing structure is made of the ground plane whose thickness is partially increased at a position corresponding to a boundary region of the wiring between the die and the mold material layer, and

a surface of the reinforcing structure opposite to the wiring is not electrically connected with another wiring.

2 . The semiconductor device according to claim 1 , wherein the reinforcing structure has a via inside the redistribution layer.

3 . The semiconductor device according to claim 1 , wherein the reinforcing structure is located at a position separated from a surface of the mold material layer via an insulating layer in the redistribution layer.

4 . The semiconductor device according to claim 1 , wherein the reinforcing structure is provided at a part of the wiring arranged in the redistribution layer so as to intersect the boundary line between the die and the mold material layer.

5 . The semiconductor device according to claim 1 , wherein the reinforcing structure is provided not entirely along the boundary line but only on a part of the wiring arranged to straddle the boundary line.