Forming structures in empty regions on wafers with dual seal ring structures
A first die includes a plurality of first transistors. A first seal ring surrounds the first die in a top view. A second die that a plurality of second transistors. A second seal ring surrounds the second die in the top view. A plurality of conductive elements extends into both the first die and the second die in the top view. The conductive elements electrically interconnect the first die with the second die. A third seal ring surrounds, in the top view, the first die, the second die, and the conductive elements.
1 . A device, comprising:
a first die that includes a plurality of first transistors;
a first seal ring that surrounds the first die in a top view;
a second die that includes a plurality of second transistors;
a second seal ring that surrounds the second die in the top view;
a plurality of conductive elements that extend into both the first die and the second die in the top view, wherein the conductive elements electrically interconnect the first die with the second die; and
a third seal ring that surrounds, in the top view, the first die, the second die, and the conductive elements, wherein the third seal ring includes a plurality of metal lines and a plurality of vias disposed between the metal lines in a side view;
wherein:
the first die or the second die includes a plurality of additional metal lines;
at least one of the additional metal lines has a first width;
a first spacing separates at least one adjacent ones of the additional metal lines;
the first width and the first spacing are measured in a first direction in the top view;
a portion of a first one of the conductive elements is located in a region outside the first seal ring and the second seal ring in the top view and has a second width that exceeds the first width;
a second spacing separates portions of adjacent ones of the conductive elements that are located outside the first seal ring and the second seal ring in the top view;
the second width and the second spacing are measured in a second direction different from the first direction in the top view; and
the second spacing exceeds the first spacing.
2 . The device of claim 1 , wherein at least one of the first seal ring and the second seal ring includes a plurality of respective further metal lines and a plurality of respective further vias disposed between the further metal lines vertically.
3 . The device of claim 2 , wherein for both the first seal ring and the second seal ring, at least one metal layer is discontinuous in the top view.
4 . The device of claim 3 , wherein with respect to the at least one metal layer:
the first seal ring includes a plurality of first gaps in the top view;
the second seal ring includes a plurality of second gaps in the top view; and
at least some of the plurality of conductive elements extend through a respective one of the first gaps and a respective one of the second gaps.
5 . The device of claim 1 , wherein the third seal ring is continuous in the top view.
6 . The device of claim 1 , wherein at least one of the conductive elements has a plurality of angular turns in the top view, or wherein at least one of the conductive elements extends in a diagonal direction.
7 . The device of claim 1 , wherein:
the first die and the second die are spaced apart in at least a first direction; and
at least some of the conductive elements extend into the first die or into the second die in at least a second direction different from the first direction.
8 . The device of claim 1 , further comprising: one or more dummy structures, one or more test structures, one or more process monitor patterns, one or more alignment marks, or one or more overlay marks that are disposed between the first die and the second die in the top view.
9 . The device of claim 1 , further comprising:
one or more additional dies outside the first seal ring and the second seal ring but within the third seal ring; and
a plurality of additional conductive elements that interconnect the one or more additional dies to the first die or to the second die.
10 . The device of claim 1 , the first die and the second die are different types of dies or have different functionalities.
11 . The device of claim 1 , wherein:
the device is a wafer-level structure on which a plurality of dies, including the first die and the second die, are implemented;
the wafer-level structure further includes at least one third die that is located outside of the third seal ring and is surrounded by a fourth seal ring in the top view; and
the third die is not electrically interconnected to any other die on the wafer-level structure.
12 . The device of claim 1 , wherein the first direction is perpendicular to the second direction in the top view.
13 . The device of claim 1 , wherein:
a ratio of the second width and the first width is in a range between about 2:1 and about 4:1; and
a ratio of the second spacing and the first spacing is in a range between about 2:1 and about 4:1.
14 . A wafer-level structure, comprising:
a plurality of integrated circuit (IC) dies, wherein at least some of the IC dies contains electrical circuitry;
a plurality of first seal ring structures that surround different ones of the IC dies in a top view;
a second seal ring structure that surrounds a subset of the IC dies in the top view, wherein the first seal ring structures surrounding the IC dies are also surrounded by the second seal ring structure in the top view, and wherein the first seal ring structures or the second seal ring structure includes a vertical stack of metal layers interconnected by vias in a side view; and
a plurality of conductive elements surrounded by the second seal ring structure in the top view, wherein the conductive elements electrically couple the subset of IC dies with one another;
wherein:
the IC dies include a plurality of metal lines that have respective first widths and are spaced apart from adjacent metal lines by respective first distances;
the first widths and the first distances are measured in a first direction in the top view;
the conductive elements have respective second widths and are spaced apart from adjacent conductive elements by respective second distances;
the second widths and the second distances are measured in a second direction different from the first direction in the top view;
at least one of the second widths is greater than at least one of the first widths; and
at least one of the second distances is greater than at least one of the first distances.
15 . The wafer-level structure of claim 14 , wherein:
at least one of the first seal ring structures surrounded by the second seal ring structure includes a discontinuity; and
the conductive elements extend into the IC dies surrounded by the second seal ring structure through the discontinuity of the first seal ring structures.
16 . The wafer-level structure of claim 14 , wherein the wafer-level structure further comprises: one or more dummy structures, one or more test structures, one or more process monitor patterns, one or more alignment marks, or one or more overlay marks that are surrounded by the second seal ring structure in the top view but are disposed outside of the first seal ring structures in the top view.
17 . The wafer-level structure of claim 14 , wherein at least some of the IC dies of the plurality of IC dies are different types of IC dies or have different functionalities than other IC dies of the plurality of IC dies.
18 . A device, comprising:
a first die that includes a plurality of first transistors;
a first seal ring located around the first die in a top view;
a second die that includes a plurality of second transistors, wherein the first die and the second die are different types of dies or have different functionalities;
a second seal ring located around the second die in the top view;
a plurality of first conductive elements that extend into both the first die and the second die in the top view, wherein the first conductive elements are electrically coupled to both the first die and the second die; and
a third seal ring disposed around the first seal ring, the second seal ring, and the first conductive elements in the top view;
wherein:
the first seal ring, the second seal ring, and the third seal ring include a plurality of respective second conductive elements and a plurality of respective vias disposed between the second conductive elements vertically in a cross-sectional side view;
at least one of the first die or the second die includes a plurality of metal lines;
at least one of the metal lines has a first width;
the metal lines are spaced apart from adjacent metal lines by a respective first spacing;
the first width and the first spacing are measured in a first direction in the top view;
at least one of the first conductive elements has a respective second width that exceeds the first width;
the first conductive elements are spaced apart from adjacent first conductive elements by a respective second spacing that exceeds the first spacing; and
the second width and the second spacing are measured in a second direction different from the first direction in the top view.
19 . The device of claim 18 , wherein at least one of the first seal ring, the second seal ring, and the third seal ring has a profile that resembles a respective rectangle in the top view.
20 . The device of claim 18 , wherein the third seal ring is continuous in the top view.