Semiconductor package including surface with reduced visual variation
A semiconductor package includes a circuit board including a wiring structure, first and second semiconductor chips disposed on the circuit board and connected to the wiring structure, a dummy chip disposed on the circuit board and positioned between the first and second semiconductor chips, and a molded member disposed on the circuit board and surrounding the first and second semiconductor chips and the dummy chip. The dummy chip may include a rounded edge between an upper surface and a side surface.
1 . A semiconductor package comprising:
a circuit board including a wiring structure;
first and second semiconductor chips on the circuit board and connected to the wiring structure;
a dummy chip on the circuit board, positioned between the first and second semiconductor chips, and having a rounded edge between an upper surface and a side surface thereof; and
a molded member on the circuit board and surrounding the first and second semiconductor chips and the dummy chip and covering upper surfaces of the first and second semiconductor chips and the upper surface of the dummy chip,
wherein the dummy chip is free of through vias extending therethrough,
wherein a vertical spacing between the upper surface of the dummy chip and an upper surface of the molded member is less than a vertical spacing between the upper surfaces of the first and second semiconductor chips and the upper surface of the molded member,
wherein the dummy chip is directly bonded to the circuit board by a bonding layer,
wherein the bonding layer is formed of a non-conductive material, and
wherein a width of the upper surface of the dummy chip is smaller than a width of a lower surface of the dummy chip.
2 . The semiconductor package of claim 1 , wherein a radius of curvature of the rounded edge of the dummy chip is about 15 μm to about 90 μm.
3 . The semiconductor package of claim 1 , wherein the rounded edge of the dummy chip comprises a convex surface.
4 . The semiconductor package of claim 1 , wherein a mounting height of the dummy chip is about 160 μm to about 180 μm, and a mounting height of the first and second semiconductor chips is about 150 μm to about 170 μm.
5 . The semiconductor package of claim 1 , wherein a mounting height of the dummy chip is about 1.05 times to about 1.30 times a mounting height of the first and second semiconductor chips.
6 . The semiconductor package of claim 1 , wherein the side surface of the dummy chip includes a plane perpendicular to an upper surface of the circuit board.
7 . The semiconductor package of claim 1 , wherein the first and second semiconductor chips are electrically connected to the wiring structure of the circuit board by a plurality of bonding wires.
8 . The semiconductor package of claim 1 , wherein a thermal expansion coefficient of the dummy chip is less than a thermal expansion coefficient of the molded member.
9 . The semiconductor package of claim 1 , wherein the side surface of the dummy chip is coplanar with a side surface of the bonding layer.