Semiconductor structure and manufacturing method therefor
The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the method, for the substrate, the first conductive type semiconductor layer, the light emitting layer and the second conductive type semiconductor layer distributed sequentially from bottom to top, the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in first predetermined regions are removed to form grooves. The second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in second predetermined regions and third predetermined regions are retained. Layers retained in second predetermined regions form light emitting units arranged in an array. Various layers retained in third predetermined regions form connection posts, each of which connects adjacent light emitting units. Widths of the third predetermined region are smaller than widths of the second predetermined region in the lateral and longitudinal direction of the array.
1 . A method for manufacturing a semiconductor structure, comprising:
providing a substrate on which a first conductive type semiconductor layer, a light emitting layer and a second conductive type semiconductor layer are sequentially formed, wherein the first conductive type is one of a N-type and a P-type and the second conductive type is the other of the N-type and the P-type; wherein a material of the first conductive type semiconductor layer, a material of the light emitting layer, or a material of the second conductive type semiconductor layer comprises a group III nitride material;
removing the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in first predetermined regions to form grooves, and retaining the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in second predetermined regions and third predetermined regions, wherein the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in the second predetermined regions form light emitting units arranged in an array, and the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in the third predetermined regions form connection posts, each of the connection posts connects adjacent light emitting units of the light emitting units; a width, in a lateral direction of the array, of each of the third predetermined regions is smaller than a width, in the lateral direction of the array, of each of the second predetermined regions; and a width, in a longitudinal direction of the array, of each of the third predetermined regions is smaller than a width, in the longitudinal direction of the array, of each of the second predetermined regions; and
removing the substrate by wet etching from the grooves, wherein an etching solution used in the wet etching removes the substrate at a greater rate in a horizontal plane direction than in a thickness direction.
2 . The method according to claim 1 , wherein for each of the third predetermined regions, the third predetermined region comprises a backbone region and a branch region, the backbone region comprises at least one of a first backbone region extending in the lateral direction or a second backbone region extending in the longitudinal direction, and the branch region is connected with the first backbone region and the second predetermined region or is connected with the second backbone region and the second predetermined region.
3 . The method according to claim 1 , wherein when removing the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in the first predetermined regions, the second conductive type semiconductor layer and the light emitting layer in the third predetermined regions are further removed, and the first conductive type semiconductor layer in the third predetermined regions is retained to form the connection posts.
4 . The method according to claim 1 , wherein after forming the first conductive type semiconductor layer, the light emitting layer and the second conductive type semiconductor layer and before removing the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in the first predetermined regions to form the grooves, or after removing the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in the first predetermined regions to form the grooves and before removing the substrate by wet etching, the method further comprising:
for each of the first predetermined regions, removing the second conductive type semiconductor layer and the light emitting layer in a part of the second predetermined region to expose a part of the first conductive type semiconductor layer; and forming a first electrode on the exposed part of the first conductive type semiconductor layer and forming a second electrode on the second conductive type semiconductor layer.
5 . The method according to claim 4 , wherein in response to determining that the first conductive type semiconductor layer is a P-type semiconductor layer, before forming the first electrode, a current diffusion layer is formed on the exposed part of the first conductive type semiconductor layer;
in response to determining that the second conductive type semiconductor layer is a P-type semiconductor layer, before forming the second electrode, a current diffusion layer is formed on the second conductive type semiconductor layer.
6 . The method according to claim 1 , wherein a light reflecting layer is formed on the substrate before the first conductive type semiconductor layer is formed; or a light reflecting layer is further formed after the second conductive type semiconductor layer is formed.
7 . The method according to claim 1 , wherein a material of the light emitting layer comprises a single quantum well material or a multiple quantum well material.
8 . The method according to claim 1 , wherein the light emitting unit comprises one or more light emitting subunits.
9 . The method according to claim 1 , wherein a material of the substrate comprises single crystal silicon, and the etching solution comprises a mixture of hydrofluoric acid, nitric acid, and acetic acid.
10 . The method according to claim 1 , wherein two ends of one of the connection posts are directly connected to two of the light emitting units, and two side walls of the one of the connection posts are directly connected to two of the grooves.