Semiconductor packages and methods of manufacturing the semiconductor packages

1 . A semiconductor package, comprising:

a package substrate having a first surface and a second surface vertically opposite to each other, and having a first mounting region and a second mounting region horizontally spaced apart from each other; and

first and second semiconductor devices respectively mounted on the first and second mounting regions on the first surface of the package substrate,

wherein the package substrate includes,

wiring patterns electrically connected to the first and second semiconductor devices;

dummy patterns electrically insulated from the first and second semiconductor devices; and

a reinforcing structure that extends along perimeters of the first and second mounting regions on the first surface of the package substrate, and bonded to at least portions of the dummy patterns and,

wherein at least a portion of the reinforcing structure is provided in a trench formed in the first surface of the package substrate, and

the trench extends along the perimeters of the first and second mounting regions and surrounds the first mounting region and the second mounting region, and a bottom surface of the trench exposes at least portions of the dummy patterns, and

wherein a thickness of the reinforcing structure is greater than a thickness of the dummy pattern.

2 . The semiconductor package of claim 1 , wherein each of the first and second semiconductor devices comprise respective conductive bumps that are bonded to bonding pads of the package substrate, and a minimum distance between the reinforcing structure and the bonding pads is within a range of 30 μm to 500 μm.

3 . The semiconductor package of claim 1 , wherein the reinforcing structure includes an embedded structure in the first surface of the package substrate, and the reinforcing structure includes a protruding structure that extends from the embedded structure and protrudes from the first surface.

4 . The semiconductor package of claim 3 , wherein a height of the protruding structure from the first surface is less than or equal to a height of lower surfaces of each of the first and second semiconductor devices from the first surface.

5 . The semiconductor package of claim 1 , wherein a width of the reinforcing structure is within a range of 200 μm to 500 μm.

6 . The semiconductor package of claim 1 , wherein the reinforcing structure includes a trapezoidal cross-sectional shape.

7 . The semiconductor package of claim 1 , wherein the reinforcing structure includes a metal material.

8 . The semiconductor package of claim 1 , wherein the first semiconductor device includes a logic semiconductor device, and

wherein the second semiconductor device includes a memory semiconductor device.

9 . The semiconductor package of claim 1 , wherein the first and second semiconductor devices and the reinforcing structure at least partially overlap each other when viewed in a plan view.

10 . A semiconductor package, comprising:

a package substrate having first and second surfaces vertically opposite to each other; and

a semiconductor device on the first surface of the package substrate,

wherein the package substrate includes,

a reinforcing structure that extends from the first surface along a perimeter of the semiconductor device;

first conductive patterns electrically connected to the semiconductor device; and

second conductive patterns bonded to the reinforcing structure and electrically insulated from the semiconductor device and,

wherein at least a portion of the reinforcing structure is provided in a trench formed in the first surface of the package substrate, and

the trench extends to surround the semiconductor device, and a bottom surface of the trench exposes at least portions of the second conductive patterns, and

wherein a thickness of the reinforcing structure is greater than a thickness of the second conductive pattern.

11 . The semiconductor package of claim 10 , wherein the semiconductor device comprises conductive bumps that are bonded respectively to bonding pads of the package substrate, and

wherein a minimum distance between the reinforcing structure and the bonding pads is in a range of 30 μm to 500 μm.

12 . The semiconductor package of claim 10 , wherein the reinforcing structure includes an embedded structure in the first surface of the package substrate and a protruding structure that protrudes from the embedded structure and extends above the first surface of the package substrate.

13 . The semiconductor package of claim 12 , wherein a height of the protruding structure above the first surface is less than or equal to a height of a lower surface of the semiconductor device from the first surface.

14 . The semiconductor package of claim 10 , wherein a horizontal width of the reinforcing structure is within a range of 200 μm to 500 μm.

15 . The semiconductor package of claim 10 , wherein the reinforcing structure includes a trapezoidal cross-sectional shape.

16 . The semiconductor package of claim 10 , wherein the reinforcing structure includes a metal material.

17 . The semiconductor package of claim 16 , wherein the reinforcing structure includes at least one of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and/or titanium (Ti).

18 . The semiconductor package of claim 10 , wherein the semiconductor device and the reinforcing structure at least partially overlap each other when viewed in a plan view.

19 . A semiconductor package, comprising:

a package substrate having first and second surfaces vertically opposite to each other; and

first and second semiconductor devices horizontally spaced apart from each other on the first surface of the package substrate,

wherein the package substrate includes,

a trench formed in the first surface and extending along a perimeter of each of the first and second semiconductor devices, the trench having an upper portion open to the first surface and a lower portion opposite to the upper portion;

wiring patterns electrically connected to the first and second semiconductor devices;

dummy patterns exposed from the lower portion of the trench and electrically insulated from the first and second semiconductor devices; and

a reinforcing structure in the trench and,

wherein the trench extends to surround the first semiconductor device and the second semiconductor device, and a bottom surface of the trench exposes at least portions of the dummy patterns, and

wherein a thickness of the reinforcing structure is greater than a thickness of the dummy pattern.