Stacked memory pop structure and packaging method thereof

1 . A stacked memory package-on-package (POP) structure, comprising:

a first package unit comprising a three-dimensional memory chip package; and

a system-in-package (SiP) package unit comprising a two-dimensional fan-out peripheral circuit,

wherein the SiP package unit of the two-dimensional fan-out peripheral circuit comprises:

a first rewiring layer having a first surface and a second surface;

at least one peripheral circuit chip arranged in two dimensions and electrically connected with the first surface of the first rewiring layer;

a second rewiring layer having a first surface and a second surface, wherein the second surface of the second rewiring layer is bonded to the at least one peripheral circuit chip;

metal connection pillars, located outside the at least one peripheral circuit chip, wherein each of the metal connection pillars has one end electrically connected with the first surface of the first rewiring layer, and another end electrically connected with the second surface of the second rewiring layer;

a second encapsulating layer, wherein the second encapsulating layer encapsulates the at least one peripheral circuit chip and the metal connection pillars; and

metal bumps, wherein the metal bumps are formed on the second surface of the first rewiring layer; and

wherein the first package unit of the three-dimensional memory chip package comprises:

a stepped configuration having a first step surface and a second step surface on the first step surface;

a first memory chip laminated on the first step surface, a second memory chip laminated on the second step surface, wherein the first memory chip is provided with a first bonding pad arranged on the first step surface, and the second memory chips is provided with a second bonding pad arranged on the second step surface;

a first wire bonding structure and a second wire bonding structure,

wherein the first wire bonding structure has one end electrically connected to the first memory chip via the first bonding pad on the first step surface and another end connected to the first surface of the second rewiring layer in the SiP package unit, and

wherein the second wire bonding structure has one end electrically connected to the second memory chip via the second bonding pad on the second step surface and another end connected to the first surface of the second rewiring layer in the SiP package unit; and

a first encapsulating layer, wherein the first encapsulating layer encapsulates the first and the second memory chips, and the first and second wire bonding structures;

and

wherein the first package unit of the three-dimensional memory chip package and the SiP package unit of the two-dimensional fan-out peripheral circuit are attached.

2 . The stacked memory POP structure according to claim 1 , wherein a bottom filler layer is provided between the at least one peripheral circuit chip and the first surface of the first rewiring layer; wherein the first and second memory chips are stacked in the stepped configuration by means of first bonding layers; and wherein the second surface of the second rewiring layer is bonded to the at least one peripheral circuit chip by a second bonding layer.

3 . The stacked memory POP structure according to claim 1 , wherein a material of the metal connection pillars comprises at least one of gold, silver, aluminum, copper; and wherein a material of the bonding pad comprises metallic aluminum.

4 . The stacked memory POP structure according to claim 1 , wherein a material of the first and second wire bonding structures comprises gold or copper; wherein a material of the first encapsulating layer comprises one of polyimide, silicone, and epoxy resin; and a material of the second encapsulating layer comprises one of polyimide, silicone, and epoxy resin.

5 . The stacked memory POP structure according to claim 1 , wherein each of the first rewiring layer and the second rewiring layer comprises a dielectric layer and a metal wiring layer; wherein a material of the dielectric layer comprises one or a combination of two or more of epoxy resin, silicone, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), silicon oxide, phosphorosilicate glass, and fluorine-containing glass, and wherein a material of the metal wiring layer comprises one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

6 . The stacked memory POP structure according to claim 1 , wherein one of the metal bumps comprises a connecting structure, which includes a solder ball, or a metal pillar, or a solder ball formed on the metal pillar, wherein the solder ball comprises one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball.

7 . A method of packaging a stacked memory package-on-package (POP) structure, comprising:

forming a system-in-package (SiP) package unit, comprising forming a two-dimensional fan-out peripheral circuit, wherein forming the two-dimensional fan-out peripheral circuit comprises:

forming a first rewiring layer having a first surface and a second surface;

forming at least one peripheral circuit chip arranged in two dimensions, wherein the at least one peripheral circuit chip is arranged to electrically connect with the first surface of the first rewiring layer;

forming a second rewiring layer having a first surface and a second surface, wherein the second surface of the second rewiring layer is bonded to the at least one peripheral circuit chip;

forming metal connection pillars, wherein the metal connection pillars are disposed outside the at least one peripheral circuit chip, wherein each of the metal connection pillars has one end electrically connected with the first surface of the first rewiring layer, and another end electrically connected with the second surface of the second rewiring layer;

forming a second encapsulating layer, wherein the second encapsulating layer encapsulates the at least one peripheral circuit chip and the metal connection pillars; and

forming metal bumps on the second surface of the first rewiring layer;

forming a first package unit, comprising forming a three-dimensional memory chip package, wherein forming thea three-dimensional memory chip package comprises;

forming a stepped configuration on the first surface of the second rewiring layer in the SiP package unit, wherein the stepped configuration comprises a first step surface and a second step surface on the first step surface;

forming a first memory chip on the first step surface and forming a second memory chip on the second step surface;

forming a first wire bonding structure having one end electrically bonded to the first memory chip via a first bonding pad on the first step surface and another end bonded to the first surface of the second rewiring layer in the SiP package unit;

forming a second wire bonding structure having one end electrically bonded to the second memory chip via a second bonding pad on the second step surface and another end bonded to the first surface of the second rewiring layer in the SiP package unit; and

encapsulating the first and the second memory chips and the first and the second wire bonding structures by a first encapsulating layer, so as to bond the first package unit of the three-dimensional memory chip package and the SiP package unit of the two-dimensional fan-out peripheral circuit together.

8 . The method of packaging the stacked memory POP structure according to claim 7 , wherein forming the SiP package unit of the two-dimensional fan-out peripheral circuit comprises:

forming the first rewiring layer having the first surface and the second surface;

electrically connecting the at least one peripheral circuit chip to the first surface of the first rewiring layer;

electrically connecting the metal connection pillars to the first surface of the first rewiring layer, wherein the metal connection pillars are formed outside of the at least one peripheral circuit chip;

encapsulating the at least one peripheral circuit chip and the metal connection pillars with the second encapsulating layer;

forming the second rewiring layer on the at least one peripheral circuit chip and the metal connection pillars, wherein the second rewiring layer is bonded to the at least one peripheral circuit chip, and the metal connection pillars are electrically connected with the second rewiring layer; and

forming the metal bumps on the second surface of the first rewiring layer.

9 . The method of packaging the stacked memory POP structure according to claim 7 , wherein the first and the second memory chips are laminated on the first surface of the second rewiring layer by a surface mount process.

10 . The method of packaging the stacked memory POP structure according to claim 7 , further comprising grinding or polishing a top surface of the first encapsulating layer and a top surface of the second encapsulating layer after forming the first encapsulating layer and the second encapsulating layer.