Semiconductor package including stacked chips and method of manufacturing the semiconductor package
A semiconductor package includes a first semiconductor chip including a substrate having a first upper surface and a first lower surface opposite thereto. The substrate has a central region and corner regions surrounding the central region. A plurality of through electrodes passes through the central region. A bonding pad is electrically connected to the through electrode and has a first height. A plurality of dummy pads respectively extend from the first upper surface on the corner regions of the substrate and have a second height that is higher than the first height. A second semiconductor chip has a second upper surface and a second lower surface opposite thereto. The second semiconductor chip is disposed on the first semiconductor chip through conductive bumps disposed on the second lower surface and electrically connected to the bonding pads.
1 . A semiconductor package, comprising:
a first semiconductor chip including a substrate having a first upper surface and a first lower surface opposite to the first upper surface, the substrate having a central region and edge regions surrounding the central region, a plurality of through electrodes penetrating through the central region of the substrate, a bonding pad electrically connected to the through electrode and having a first height from the first upper surface, and a plurality of dummy pads respectively extending from the first upper surface on the edge regions of the substrate and having a second height that is higher than the first height;
a second semiconductor chip having a second upper surface and a second lower surface opposite to the second upper surface, the second semiconductor chip disposed on the first semiconductor chip via conductive bumps that are disposed on the second lower surface and are electrically connected to the bonding pads; and
an adhesive configured to fill a space between the first and second semiconductors in the central region excluding corner regions of the substrate.
2 . The semiconductor package of claim 1 , wherein each of the plurality of dummy pads is in contact with the second lower surface of the second semiconductor chip.
3 . The semiconductor package of claim 1 , wherein the second height of each of the plurality of dummy pads is within a range of 3 μm to 30 μm.
4 . The semiconductor package of claim 1 , wherein the plurality of dummy pads are disposed in four corner regions on the first upper surface.
5 . The semiconductor package of claim 4 , wherein the number of the dummy pads of the plurality of dummy pads that are disposed in each of the corner regions is within a range of 10 to 100.
6 . The semiconductor package of claim 1 , wherein a diameter of each of the plurality of dummy pad is within a range of 10 μm to 50 μm.
7 . The semiconductor package of claim 1 , wherein each of the plurality of dummy pads includes copper (Cu), aluminum (Al), tungsten, nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and/or titanium (Ti).
8 . The semiconductor package of claim 1 , wherein each of the plurality of dummy pad includes:
a support bar extending in a vertical direction from the first upper surface; and
a support pad disposed on the support bar and having a second diameter that is greater than a first diameter of the support bar.
9 . The semiconductor package of claim 1 , further comprising:
a third semiconductor chip disposed on the second semiconductor chip,
wherein the second semiconductor chip further includes a plurality of second dummy pads respectively extending from the second upper surface in a vertical direction to support a lower surface of the third semiconductor chip.