Semiconductor die package and methods of manufacturing
Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.
1 . A method, comprising:
forming a seed layer on a release film layer;
forming a pad structure on the seed layer;
forming a pillar structure on the seed layer;
removing portions of the seed layer that are not covered by the pad structure and the pillar structure;
placing a first integrated circuit die over the pad structure such that the pad structure is submerged in a first bonding film layer; and
placing a second integrated circuit die over the release film layer between the pad structure and the pillar structure using a second bonding film layer.
2 . The method of claim 1 ,
wherein forming the seed layer on the release film layer comprises:
forming a layer of a titanium-copper material on the release film layer, and
wherein forming the pad structure on the seed layer comprises:
plating a layer of copper material on the layer of titanium-copper material, and
forming the pad structure from the layer of copper material using a photolithography process.
3 . The method of claim 1 ,
wherein a first viscosity of the first bonding film layer, during the placing of the first integrated circuit die over the pad structure, is lesser relative to a second viscosity of the second bonding film layer during the placing of the second integrated circuit die on the release film layer.
4 . The method of claim 1 ,
wherein placing the first integrated circuit die over the pad structure comprises:
heating the first bonding film layer to an elevated temperature; and
placing the first integrated circuit die over the pad structure while the first bonding film layer is at the elevated temperature.
5 . The method of claim 1 ,
wherein placing the second integrated circuit die on the release film layer comprises:
heating the second bonding film layer to an elevated temperature; and
placing the second integrated circuit die on the release film layer while the second bonding film layer is at the elevated temperature.
6 . The method of claim 1 , further comprising:
connecting the pillar structure and a first solder connection structure; and
connecting the pad structure and a second solder connection structure.
7 . The method of claim 1 , further comprising:
forming the first bonding film layer on the first integrated circuit die prior to placing the first integrated circuit die over the pad structure.
8 . The method of claim 7 ,
wherein forming the first bonding film layer on the first integrated circuit die comprises:
dicing a b-stage type of a conformal bonding film into a segment; and
placing the segment on the first integrated circuit die.
9 . A method, comprising:
forming a first pad structure on a first portion of a seed layer;
forming a connection structure on a second portion of the seed layer, wherein the second portion of the seed layer is laterally spaced from the first portion of the seed layer;
forming a first integrated circuit die over the first pad structure; and
forming a second integrated circuit die between the first pad structure and the connection structure,
wherein the second integrated circuit die is laterally spaced from the connection structure and the first integrated circuit die.
10 . The method of claim 9 , wherein a height of the connection structure is greater than a height of the first pad structure.
11 . The method of claim 9 , a width of the first pad structure is in a range of approximately 50 μm to approximately 300 μm.
12 . The method of claim 9 , further comprising:
forming, over at least one of the first integrated circuit die and the second integrated circuit die, at least one of a layer of polyimide material and a second pad structure.
13 . The method of claim 9 , further comprising:
forming a mold compound surrounding the connection structure, the first integrated circuit die, and the second integrated circuit die.
14 . The method of claim 13 , wherein the mold compound comprises at least a first portion, between the first integrated circuit and the second integrated circuit, and a second portion, between the second integrated circuit and the connection structure.
15 . The method of claim 9 , further comprising:
forming an interconnection structure over the connection structure, the first integrated circuit die, and the second integrated circuit die; and
forming one or more connection structures on the interconnection structure.
16 . A method, comprising:
forming a mold component comprising:
a first pad structure,
a first connection structure, wherein the first connection structure is laterally spaced from the first pad structure, and wherein the first connection structure resides on a same horizontal plane as the first pad structure,
a first integrated circuit die over the first pad structure;
a second integrated circuit die between the first pad structure and the first connection structure,
wherein the second integrated circuit die is laterally spaced from the first connection structure and the first integrated circuit die;
forming a first interconnection structure over the mold component; and
forming one or more connection components on the first interconnection structure.
17 . The method of claim 16 , further comprising:
forming an underfill material over the mold component,
wherein the underfill material and the first interconnection structure are formed over opposing sides of the mold component.
18 . The method of claim 17 , further comprising:
forming a second interconnection structure over the underfill material, wherein the second interconnection structure comprises an electrically conductive trace.
19 . The method of claim 18 , wherein the second interconnection structure further comprises a second connection structure connecting the first connection structure to the electrically conductive trace.
20 . The method of claim 19 , further comprising:
one or more of:
a third die, over the second interconnection structure, connected to the electrically conductive trace, or
a fourth die, over the second interconnection structure, connected to a pad structure in the second interconnection structure.