ESD implant following spacer deposition
View Patent ↗One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.
1. A method of forming non-volatile semiconductor memory device, comprising:
providing a semiconductor substrate having a core region comprising memory cells and a peripheral region, wherein word lines in the core region connecting the memory cells are spaced apart by about 1 μm or less;
forming one or more insulating layers for one or more electrostatic discharge protection transistors and one or more other transistors in the peripheral region;
forming a poly layer over the insulating layers;
patterning electrostatic discharge protection transistors and other transistors from the insulating layers and the poly layer;
depositing spacer material over the electrostatic discharge protection transistors and the other transistors;
etching the spacer material to form spacers; and
with the spacers in place and without masking the other transistors, heavily doping source and drain regions for the electrostatic discharge protection transistors to provide channel lengths for the electrostatic protection transistors of about 1 μm or less.
2. The method of claim 1 , wherein heavily doping source and drain regions involves implanting with one of arsenic and phosphorus at about 5×10 14 atoms/cm 2 to about 7×10 15 atoms/cm 2 at an energy from about 60 keV to about 100 keV.
3. The method of claim 1 , wherein the non-volatile semiconductor memory device is a SONOS type flash memory device.
4. The method of claim 3 , wherein the flash memory device comprises a virtual ground array structure and SONOS type memory cells.
5. The method of claim 1 , wherein heavily doping source and drain regions involves implanting with one of arsenic and phosphorus at about 1×10 14 atoms/cm 2 to about 1×10 16 atoms/cm 2 at an energy from about 60 keV to about 100 keV.
6. A method of forming non-volatile semiconductor memory device, comprising:
providing a semiconductor substrate having a core region comprising memory cells and a peripheral region, wherein word lines in the core region connecting the memory cells are spaced apart by about 1 μm or less;
forming one or more insulating layers for one or more electrostatic discharge protection transistors and one or more other transistors in the peripheral region;
forming a poly layer over the insulating layers;
patterning electrostatic discharge protection transistors and other transistors from the insulating layers and the poly layer;
lightly doping source and drain regions for the electrostatic discharge protection transistors with one of arsenic, boron, and phosphorus at about 1×10 11 atoms/cm 2 to about 1×10 14 atoms/cm 2 at an energy from about 20 keV to about 80 keV;
depositing spacer material over the electrostatic discharge protection transistors and the other transistors;
etching the spacer material to form spacers; and
with the spacers in place and without masking the other transistors, heavily doping source and drain regions for the electrostatic discharge protection transistors with one of arsenic and phosphorus at about 1×10 14 atoms/cm 2 to about 1×10 16 atoms/cm 2 at an energy from about 60 keV to about 100 keV to provide channel lengths for the electrostatic protection transistors of about 0.25 μm or less.
7. A method of forming non-volatile semiconductor memory device, comprising:
providing a semiconductor substrate having a core region comprising memory cells and a peripheral region, wherein word lines in the core region connecting the memory cells are spaced apart by about 1 μm or less;
forming one or more insulating layers for one or more electrostatic discharge protection transistors and one or more other transistors in the peripheral region;
forming a poly layer over the insulating layers;
patterning electrostatic discharge protection transistors and other transistors from the insulating layers and the poly layer;
lightly doping source and drain regions for the electrostatic discharge protection transistors with one of arsenic, boron, and phosphorus at about 1×10 11 atoms/cm 2 to about 1×10 14 atoms/cm 2 at an energy from about 20 keV to about 80 keV;
depositing spacer material over the electrostatic discharge protection transistors and the other transistors;
etching the spacer material to form spacers; and
with the spacers in place and without masking the other transistors, heavily doping source and drain regions for the electrostatic discharge protection transistors with one of arsenic and phosphorus at about 5×10 14 atoms/cm 2 to about 7×10 15 atoms/cm 2 at an energy from about 60 keV to about 100 keV to provide channel lengths for the electrostatic protection transistors of about 0.25 μm or less.
8. The method of claim 1 , wherein the channel lengths of the electrostatic protection transistors are about 0.25 μm or less.
9. The method of claim 1 , wherein the channel lengths of the electrostatic protection transistors are about 0.15 μm or less.
10. The method of claim 1 , wherein the word lines in the core region connecting the memory cells are spaced apart by about 0.2 μm to about 0.75 μm.
11. The method of claim 2 , wherein heavily doping source and drain regions for the electrostatic discharge protection transistors comprises doping with arsenic.
12. The method of claim 2 , wherein heavily doping source and drain regions for the electrostatic discharge protection transistors comprises doping with phosphorus.
13. The method of claim 6 , wherein the non-volatile semiconductor memory device is a SONOS type flash memory device.
14. The method of claim 6 , wherein heavily doping source and drain regions for the electrostatic discharge protection transistors comprises doping with arsenic.
15. The method of claim 6 , wherein the channel lengths of the electrostatic protection transistors are about 0.15 μm or less.
16. The method of claim 6 , wherein the word lines in the core region connecting the memory cells are spaced apart by about 0.2 μm to about 0.75 μm.
17. The method of claim 7 , wherein the non-volatile semiconductor memory device is a SONOS type flash memory device.
18. The method of claim 7 , wherein the channel lengths of the electrostatic protection transistors are about 0.15 μm or less.
19. The method of claim 7 , wherein the word lines in the core region connecting the memory cells are spaced apart by about 0.2 μm to about 0.75 μm.
20. The method of claim 7 , wherein heavily doping source and drain regions for the electrostatic discharge protection transistors comprises doping with phosphorus.