IP Library Granted Patent US 7,199,653
Granted Patent B2
US 7,199,653 · App. 11/335,513 · Granted Apr 3, 2007

Semiconductor device with operation mode set by external resistor

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Quick Facts
Patent No.
US 7,199,653
App. No.
11/335,513
Filed
Jan 20, 2006
Granted
Apr 3, 2007
Kind
B2
Examiner
PERT, EVAN T
Art Unit
2826
USPC
327/564
Abstract

A semiconductor device capable of setting a large number of operation modes with a single external terminal, while ensuring a stable operation mode regardless of fluctuations in the power supply voltage. The semiconductor device includes an internal circuit having a plurality of modes, an external terminal, an external resistor connected to the external terminal, and a current detection circuit for generating a setting signal based on the current flowing through the external resistor. The internal circuit includes a mode setting circuit which sets one of the operation modes of the internal circuit in response to the setting signal.

Claims (23)

1. A semiconductor device comprising:

an internal circuit having a plurality of operation modes, wherein the internal circuit includes a mode setting circuit for setting one of the operation modes of the internal circuit in response to a setting signal;

an external terminal;

an external resistor connected to the external terminal; and

a current detection circuit for generating the setting signal based on current flowing through the external resistor.

2. The semiconductor device according to claim 1 , wherein the current detection circuit includes:

a plurality of internal resistors;

a current generation circuit for supplying the same current to each of the external resistor and the internal resistors; and

a plurality of comparators respectively connected to the plurality of internal resistors, each of the comparators comparing a voltage generated at the corresponding internal resistor with a reference voltage to generate the setting signal.

3. The semiconductor device according to claim 2 , wherein the plurality of internal resistors are connected in parallel to the current generation circuit.

4. The semiconductor device according to claim 2 , wherein the plurality of internal resistors are connected in series to the current generation circuit.

5. The semiconductor device according to claim 2 , wherein the current generation circuit and the comparators include a power consumption reducing means, for stopping the flow of current in response to a power-down signal, and a latch circuit, for holding the setting signal of the comparators.

6. The semiconductor device according to claim 1 , wherein the internal circuit includes a PLL circuit having a frequency divider, and the frequency divider includes the mode setting circuit.

7. The semiconductor device according to claim 1 , wherein the internal circuit includes a PLL circuit having a phase comparator, and the phase comparator includes the mode setting circuit.

8. The semiconductor device according to claim 1 , wherein the internal circuit includes a PLL circuit having a charge pump, and the charge pump includes the mode setting circuit.

9. The semiconductor device according to claim 1 , wherein the internal circuit includes a PLL circuit having a loop filter, and the loop filter includes the mode setting circuit.

10. The semiconductor device according to claim 1 , wherein the internal circuit includes a PLL circuit having a voltage-controlled oscillator, and the voltage-controlled oscillator includes the mode setting circuit.

11. The semiconductor device according to claim 10 , wherein the voltage-controlled oscillator includes:

a voltage-current conversion circuit;

a variable current circuit connected to the voltage-current conversion circuit; and

a current-controlled oscillator connected to the variable current circuit, the variable current circuit including the mode setting circuit.

12. The semiconductor device according to claim 1 , wherein the internal circuit and the current detection circuit are formed on a single chip.

13. The semiconductor device according to claim 12 , wherein the chip and the external resistor are packaged together.