Semiconductor device and a method of manufacturing the same
View Patent ↗A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch. In the semiconductor device, impurity ions having a p-type conduction, e.g. B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p + -type semiconductive region and in contact with the p + -type semiconductive region and an n − -type single crystal silicon layer and that has an impurity concentration lower than the p + -type semiconductive region. An n-type semiconductive region is formed in the n − -type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n − -type single crystal silicon layer.
1. A semiconductor device including a trench gate type MISFET, the device comprising;
a semiconductor substrate;
a drain electrode of the trench gate type MISFET formed on a back surface of the semiconductor substrate;
a first semiconductor layer formed over a main surface of the semiconductor substrate;
a plurality of channel layers of the trench gate type MISFET, each formed over the first semiconductor layer;
a plurality of source regions of the trench gate type MISFET formed over the channel layers, respectively;
a plurality of gate trenches of the trench gate type MISFET formed between coplanar, adjacent source regions respectively and reaching the first semiconductor layer;
a plurality of gate insulating films of the trench gate type MISFET formed in the gate trenches respectively;
a plurality of gate electrodes of the trench gate type MISFET formed on the gate insulating films, respectively;
a first insulating film formed over the source regions and gate electrodes;
a plurality of contact grooves each formed in the first insulating film between coplanar, adjacent gate electrodes and in contact with the channel layer;
a plurality of semiconductive regions formed under bottoms of the contact grooves respectively, and in contact with the bottom of the contact grooves;
a source electrode formed in the contact grooves and electrically connected with the semiconductive regions,
wherein the semiconductor substrate, first semiconductor layer and source regions have a first conduction type;
wherein the channel layer and semiconductive regions have a second conduction type opposite to the first conduction type;
wherein the semiconductive regions have an impurity concentration higher than the channel layer;
wherein bottoms of the semiconductive regions are closer to the drain electrode, compared with a bottom of the channel layer.
2. A semiconductor device according to claim 1 , wherein the first semiconductor layer is formed by an epitaxial growing method.
3. A semiconductor device according to claim 1 , wherein the plurality of gate trenches are integrally formed;
the plurality of gate electrodes are integrally formed; and
the plurality of source regions are electrically connected.
4. A semiconductor device according to claim 1 , wherein the first and second conduction types are n-type and p-type respectively.
5. A semiconductor device including a MISFET, the device comprising:
a semiconductor substrate;
a drain electrode of the MISFET formed on a back surface of the semiconductor substrate;
a first semiconductor layer formed over a main surface of the semiconductor substrate;
a plurality of channel layers of the MISFET, each formed over the first semiconductor layer;
a plurality of source regions of the MISFET formed over the channel layers, respectively;
a plurality of gate insulating films of the MISFET formed between coplanar, adjacent source regions respectively;
a plurality of gate electrodes of the MISFET formed on the gate insulating films, respectively;
a first insulating film formed over the source regions and gate electrodes;
a plurality of contact grooves each formed in the first insulating film between coplanar, adjacent gate electrodes and in contact with the channel layer;
a plurality of semiconductive regions formed under bottoms of the contact grooves respectively, and in contact with the bottom of the contact grooves;
a source electrode formed in the contact grooves and electrically connected with the semiconductive regions,
wherein the semiconductor substrate, first semiconductor layer and source regions have a first conduction type;
wherein the channel layer and semiconductive regions have a second conduction type opposite to the first conduction type;
wherein the semiconductive regions have an impurity concentration higher than the channel layer;
wherein bottoms of the semiconductive regions are closer to the drain electrode, compared with a bottom of the channel layer.
6. A semiconductor device according to claim 5 , wherein the first semiconductor layer is formed by an epitaxial growing method.