IP Library › Granted Patent US 7,288,835
Granted Patent B2
US 7,288,835 · App. 11/276,941 · Granted Oct 30, 2007

Integrated circuit package-in-package system

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Quick Facts
Patent No.
US 7,288,835
App. No.
11/276,941
Filed
Mar 17, 2006
Granted
Oct 30, 2007
Kind
B2
Art Unit
2815
USPC
257/685
Abstract

An integrated circuit package-in-package system is provided forming a first integrated circuit package having a first interface, stacking a second integrated circuit package having a second interface above the first integrated circuit package, fitting the first interface and the second interface, and attaching a third integrated circuit package on the second integrated circuit package.

Claims (118)

1. An integrated circuit package-in-package system comprising:

forming a first integrated circuit package having a first interface;

stacking a second integrated circuit package having a second interface above the first integrated circuit package and including:

forming a cavity in a first encapsulation of the second integrated circuit package, and

forming the second interface defined by the cavity;

fitting the first interface and the second interface;

forming a second encapsulation to cover the first integrated circuit package and second integrated circuit package;

forming a recess in the second encapsulation exposed a substrate of the second integrated circuit package;

attaching a third integrated circuit package on the second integrated circuits package; and

connecting the third integrated circuit package to the substrate.

2. The system as claimed in claim 1 wherein fitting the first interface and the second interface comprises:

forming the first interface defined by a first electrical interface pattern on a first substrate of the first integrated circuit package;

forming the second interface defined by a second electrical interface pattern on a second substrate of the second integrated circuit package; and

mating the first electrical interface pattern and the second electrical interface pattern.

3. The system as claimed in claim 1 wherein:

forming the first integrated circuit package having the first interface comprises:

forming the first interface defined by a first electrical interface pattern on a first substrate of the first integrated circuit package;

stacking the second integrated circuit package having the second interface further comprises:

forming the second interface defined by a second electrical interface pattern on a second substrate of the second integrated circuit package;

fitting the first interface and the second interface further comprises:

mating the first electrical interface pattern and the second electrical interface pattern;

attaching the third integrated circuit package on the second integrated circuit package further comprises:

stacking the third integrated circuit package having a third electrical interface pattern on the second integrated circuit package; and

further comprising:

stacking a fourth integrated circuit package having a fourth electrical interface pattern on the third integrated circuit package;

mating the third electrical interface pattern and the fourth electrical interface pattern; and

encapsulating the first integrated circuit package, the second integrated circuit package, the third integrated circuit package, and the fourth integrated circuit package.

4. The system as claimed in claim 1 wherein:

forming the first integrated circuit package having the first interface comprises:

forming the first interface defined by a first electrical interface pattern on a first substrate of the first integrated circuit package;

stacking the second integrated circuit package having the second interface further comprises:

forming the second interface defined by a second electrical interface pattern on a second substrate of the second integrated circuit package;

fitting the first interface and the second interface further comprises:

mating the first electrical interface pattern and the second electrical interface pattern; and

attaching the third integrated circuit package on the second integrated circuit package further comprises:

stacking the third integrated circuit package having a third electrical interface pattern on the second integrated circuit package; and

further comprising:

forming an encapsulation to cover the first integrated circuit package, the second integrated circuit package, and the third integrated circuit package;

forming a recess in the encapsulation to expose the third electrical interface pattern on a third substrate of the third integrated circuit package;

stacking a fourth integrated circuit package having a fourth electrical interface pattern in the recess on the third integrated circuit package; and

mating a portion of the third electrical interface pattern and the fourth electrical interface pattern.

5. An integrated circuit package-in-package system comprising:

forming a first integrated circuit package having a first interface and including:

forming the first interface defined by a first electrical interface pattern on a first substrate of the first integrated circuit package;

stacking a second integrated circuit package having a second interface above the first integrated circuit package and including:

forming the second integrated circuit package with a second integrated circuit die having a second electrical interface pattern, and

forming the second interface defined by the second electrical interface pattern;

fitting the first interface and the second interface;

electrically connecting the first integrated circuit package and the second integrated circuit package;

attaching a third integrated circuit package on the second integrated circuit package;

forming an encapsulation to cover the first integrated circuit package, the second integrated circuit package, and the third integrated circuit package;

forming a recess in the encapsulation to expose the third electrical interface pattern on a third substrate of the third integrated circuit package;

stacking a fourth integrated circuit package having a fourth electrical interface pattern in the recess on the third integrated circuit package; and

mating a portion of the third electrical interface pattern and the fourth electrical interface pattern.

6. The system as claimed in claim 5 wherein attaching the third integrated circuit package on the second integrated circuit package includes electrically connecting the third integrated circuit package and the second integrated circuit package.

7. The system as claimed in claim 5 further comprising mounting the first integrated circuit package on a package substrate.

8. The system as claimed in claim 5 further comprising electrically connecting the first integrated circuit package and a package substrate.

9. An integrated circuit package-in-package system comprising:

a first integrated circuit package having a first interface;

a second integrated circuit package having a second interface above the first integrated circuit package and including:

a cavity in a first encapsulation of the second integrated circuit package, and the second interface defined by the cavity;

the first interface fitted with the second interface;

a third integrated circuit package on the second integrated circuit package;

a second encapsulation to cover the first integrated circuit package and second integrated circuit package;

a recess in the second encapsulation exposing a substrate of the second integrated circuit package; and

the third integrated circuit package connected to the substrate.

10. The system as claimed in claim 9 wherein the first interface with the second interface comprises:

the first interface defined by a first electrical interface pattern on a first substrate of the first integrated circuit package;

the second interface defined by a second electrical interface pattern on a second substrate of the second integrated circuit package; and

the first electrical interface pattern mated with the second electrical interface pattern.

11. The system as claimed in claim 9 wherein:

the first integrated circuit package having the first interface comprises:

the first interface defined by a first electrical interface pattern on a first substrate of the first integrated circuit package;

the second integrated circuit package having the second interface further comprises:

the second interface defined by a second electrical interface pattern on a second substrate of the second integrated circuit package;

the first interface fitted with the second interface further comprises:

the first electrical interface pattern mated with the second electrical interface pattern; and

the third integrated circuit package on the second integrated circuit package further comprises:

the third integrated circuit package having a third electrical interface pattern on the second integrated circuit package; and

further comprising:

a fourth integrated circuit package having a fourth electrical interface pattern on the third integrated circuit package;

the third electrical interface pattern mated with the fourth electrical interface pattern; and

an encapsulation to cover the first integrated circuit package, the second integrated circuit package, the third integrated circuit package, and the fourth integrated circuit package.

12. The system as claimed in claim 9 wherein:

the first integrated circuit package having the first interface comprises:

the first interface defined by a first electrical interface pattern on a first substrate of the first integrated circuit package;

the second integrated circuit package having the second interface further comprises:

the second interface defined by a second electrical interface pattern on a second substrate of the second integrated circuit package;

the first interface fitted with the second interface further comprises:

the first electrical interface pattern mated with the second electrical interface pattern; and

the third integrated circuit package on the second integrated circuit package further comprises:

the third integrated circuit package having a third electrical interface pattern on the second integrated circuit package; and

further comprising:

an encapsulation to cover the first integrated circuit package, the second integrated circuit package, and the third integrated circuit package,

a recess in the encapsulation to expose the third electrical interface pattern on a third substrate of the third integrated circuit package,

a fourth integrated circuit package having a fourth electrical interface pattern in the recess on the third integrated circuit package, and

a portion of the third electrical interface pattern mated with the fourth electrical interface pattern.

13. The system as claimed in claim 9 wherein:

the first integrated circuit package having the first interface has a first integrated circuit die;

the second integrated circuit package having the second interface above the first integrated circuit package has a second integrated circuit die;

the first interface fitted with the second interface is a compatible interface; and

the third integrated circuit package on the second integrated circuit package has a third integrated circuit die; and

further comprising:

the first integrated circuit package electrically connected to the second integrated circuit package.

14. The system as claimed in claim 13 wherein:

the first integrated circuit package having the first interface comprises:

the first interface defined by a first electrical interface pattern on a first substrate of the first integrated circuit package; and

the second integrated circuit package having the second interface above the first integrated circuit package further comprises:

the second integrated circuit package with a second integrated circuit die having a second electrical interface pattern, and

the second interface defined by the second electrical interface pattern; and

further comprising:

an encapsulation to cover the first integrated circuit package, the second integrated circuit package, and the third integrated circuit package;

a recess in the encapsulation to expose the third electrical interface pattern on a third substrate of the third integrated circuit package;

a fourth integrated circuit package having a fourth electrical interface pattern in the recess on the third integrated circuit package; and

a portion of the third electrical interface pattern mated with the fourth electrical interface pattern.

15. The system as claimed in claim 13 wherein the third integrated circuit package on the second integrated circuit package includes an interconnect between the third integrated circuit package and the second integrated circuit package.

16. The system as claimed in claim 13 further comprising the first integrated circuit package on a package substrate.

17. The system as claimed in claim 13 further comprising an interconnect between the first integrated circuit package and a package substrate.