Flash memory programming using an indication bit to interpret state
View Patent ↗Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current per window during programming.
1. A non-volatile memory device comprising:
an array of non-volatile memory cells comprising
a plurality of groups of memory cells in which the memory cells in the plurality of groups of memory cells include SONOS (silicon-oxide-nitride-oxide-silicon) type NOR memory cells that store two or more bits per memory cell; and
a plurality of memory cells used to respectively indicate whether a programmed/non-programmed state of the memory cells in one of the groups is interpreted as a logic zero or a logic one.
2. The memory device of claim 1 , further comprising:
control logic configured to dynamically determine whether the programmed/non-programmed state of the memory cells in a first one of the groups are interpreted as a logic zero or a logic one.
3. The memory device of claim 2 , wherein when dynamically determining, the control logic is configured to analyze logic states of bits that are to be written to the memory cells in the first group.
4. The memory device of claim 3 , wherein when analyzing logic states, the control logic is configured to determine the logic state of a minority of the bits that are to be written to the first group.
5. The memory device of claim 1 , wherein the array of non-volatile memory cells includes:
a plurality of bit lines each connected to source or drain regions of the memory cells; and
a plurality of word lines, arranged orthogonally to the bit lines, each word line being connected to gate regions of the memory cells.
6. The memory device of claim 1 , wherein each of the groups is associated with 64 memory cells.
7. The memory device of claim 1 , wherein the memory cells within a group are programmed simultaneously.
8. A method for writing data to memory cells of a non-volatile memory device comprising:
receiving a predetermined number of bits that are to be written;
analyzing the predetermined number of bits to determine a logic state of a minority of the bits;
writing each of the bits to a memory cell in the memory device by programming those that correspond to the minority of the bits, the memory cell including a SONOS (silicon-oxide-nitride-oxide-silicon) type NOR memory cell that stores two or more bits per memory cell; and
writing an indication bit that indicates the determined logic state of the minority of the bits.
9. The method of claim 8 , wherein the writing each of the bits and the writing the indication bit are performed simultaneously.
10. The method of claim 8 , wherein programming those of the predetermined number of bits that correspond to the minority of the bits includes storing charge in respective charge storage layers of memory cells corresponding to the bits.
11. The method of claim 8 , wherein the predetermined number of bits is 64 bits.
12. The method of claim 8 , further comprising:
writing a separate indication bit for a plurality of portions of the predetermined number of bits.
13. The method of claim 8 , further comprising:
performing an erase operation before writing each of the bits.
14. A semiconductor memory device comprising:
an array of non-volatile memory cells organized as
a plurality of memory cell windows, and
a plurality of indication bit memory cells used to respectively indicate whether a programmed/non-programmed state of the memory cells in one of the memory cell windows is interpreted as a logic zero or a logic one; and
control logic configured to determine a programmed state of each indication bit memory cell based on an analysis of intended logic states of the non-volatile memory cells associated with one of the memory windows,
wherein the memory cells of the array of non-volatile memory cells include SONOS (silicon-oxide-nitride-oxide-silicon) type NOR memory cells that store two or more bits per memory cell.
15. The semiconductor device of claim 14 , wherein the programmed states of the indication bit memory cells are determined based on a minimum number of memory cells within a memory cell window that are needed to be programmed.
16. The semiconductor device of claim 14 , wherein the arr ay of non-volatile memory cells includes:
a plurality of bit lines each connected to source or drain regions of the non-volatile memory cells; and
a plurality of word lines, arranged orthogonally to the bit lines, each word line being connected to gate regions of the non-volatile memory cells.
17. The semiconductor memory device of claim 14 , wherein the non-volatile memory cells within one of the memory cell windows are programmed simultaneously.