IP Library › Granted Patent US 7,298,178
Granted Patent B1
US 7,298,178 · App. 11/427,717 · Granted Nov 20, 2007

Clock-generator architecture for a programmable-logic-based system on a chip

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Quick Facts
Patent No.
US 7,298,178
App. No.
11/427,717
Filed
Jun 29, 2006
Granted
Nov 20, 2007
Kind
B1
Examiner
LUU, AN T
Art Unit
2816
USPC
327/10
Abstract

A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Claims (14)

1. A programmable system-on-a-chip integrated circuit device comprising:

an oscillator circuit;

a programmable logic block;

a clock conditioning circuit selectively coupleable to the programmable logic block and the oscillator circuit, wherein the clock conditioning circuit includes a phase locked loop, the phase locked loop includes a frequency divider circuit in its feedback loop;

a real-time clock selectively coupleable to the programmable logic block, and the oscillator circuit; and

a non-volatile memory, wherein the frequency divider circuit is configurable from at least one of the programmable logic block and the non-volatile memory.

2. The device of claim 1 , wherein the phase locked loop includes a frequency divider circuit driving its input.

3. The device of claim 1 , wherein the phase locked loop drives a frequency divider circuit from its output.

4. The device of claim 1 , wherein the oscillator circuit is an RC oscillator circuit.

5. The device of claim 4 , further including an external oscillator input, wherein said clock conditioning circuit is selectively coupleable to the external oscillator input.

6. The device of claim 1 , wherein the oscillator circuit is a crystal oscillator circuit.

7. The device of claim 6 , further including an external oscillator input selectively coupleable to the clock conditioning circuit.

8. The device of claim 1 , further including a clock output pad selectively coupleable to one of the programmable logic block and the oscillator circuit.

9. The device of claim 1 , wherein the real-time clock includes a match output and further including a voltage-regulator controller circuit coupled to an I/O pad and to the match output for controlling the signal to an external voltage regulator in response to a signal on the match output.