Edge seal for improving integrated circuit noise isolation
View Patent ↗An edge seal structure and fabrication method are described. The edge seal structure includes a high impedance substrate containing a base material and a grounded floating edge seal that is on the substrate but is isolated from the base material. The edge seal contacts a first doped well in the substrate that has the same conductivity type as and is more heavily doped than the base material. The first doped well is in a second doped well that has a different conductivity type than the first doped well. The first and second doped wells and the base material form back-to-back series connected diodes. The wells are effectively connected to power and ground such that the diodes are reverse-biased. The edge seal is formed by a stack of conductive layers, at least some of which are surrounded by a stack of insulating layers.
1. An integrated circuit edge seal structure comprising:
a substrate containing a base material, the substrate comprising a first doped well disposed in the base material and a second doped well in which the first doped well is disposed, wherein the first and second doped wells have different conductivity types to form a first diode, the second doped well and the substrate have different conductivity types to form a second diode, and the first and second diodes are connected to ground and a power supply such that the first and second diodes are reversed biased; and
a conductive edge seal disposed on the substrate, the edge seal electrically isolated from the base material.
2. The edge seal structure of claim 1 , further comprising a resistor through which each of the first and second diodes is connected to ground or the power supply, respectively.
3. The edge seal structure of claim 1 , wherein the edge seal comprises a stack of conductive layers at least some of which are surrounded by a stack of insulating layers.
4. The edge seal structure of claim 1 , wherein the edge seal is grounded.
5. An integrated circuit edge seal structure comprising:
a substrate containing a base material, wherein the substrate comprises a first doped well disposed in the base material, a second doped well in which the first doped well is disposed, and a third doped well disposed in the second doped well adjacent to the first doped well, the first and second doped wells having different conductivity types to form a first diode, the second and third doped wells having the same conductivity type, and the third doped well more heavily doped than the second doped well; and
a conductive edge seal disposed on the substrate, the edge seal electrically isolated from the base material.
6. An integrated circuit edge seal structure comprising:
a substrate containing a base material, wherein the substrate comprises a first doped well disposed in the base material, a second doped well in which the first doped well is disposed, and a third doped well disposed in the second doped well, the first and second doped wells having different conductivity types to form a first diode, the first doped well disposed in the third doped well, the first and third doped wells having the same conductivity type, and the first doped well more heavily doped than the third doped well; and
a conductive edge seal disposed on the substrate, the edge seal electrically isolated from the base material.
7. The edge seal structure of claim 6 , wherein the second doped well has a different conductivity type than the substrate to form a second diode.
8. A chip comprising:
a substrate containing a first doped well disposed inside a second doped well, the substrate and the first doped well having a different conductivity type than the second doped well, wherein the first doped well and the second doped well form a first diode, the second doped well and the substrate form a second diode, and the first and second diodes are connected to ground and a power supply such that the first and second diodes are reverse biased;
an edge seal containing at least two conductive layers on the substrate, the at least two conductive layers including a contact layer that contacts the first doped well; and
an integrated circuit on the substrate at least partially surrounded by the edge seal.
9. The chip of claim 8 , further comprising a resistor through which each of the first and second diodes is connected to ground or the power supply, respectively.
10. The chip of claim 8 , wherein the substrate contains a third doped well disposed in the second doped well adjacent to the first doped welt, the second and third doped wells having the same conductivity type, the third doped well more heavily doped than the second doped well.
11. The chip of claim 8 , wherein the substrate contains a third doped well disposed in the second doped well, the first well disposed in the third doped well, the first and third doped wells having the same conductivity type, the first doped well more heavily doped than the third doped well.
12. The chip of claim 8 , wherein the substrate is a high impedance substrate.
13. The chip of claim 8 , wherein the edge seal is grounded.