Analog digital converter (ADC) having improved stability and signal to noise ratio (SNR)
View Patent ↗A sigma delta (ΣΔ) analog to digital converter (ADC) that compensates for the adverse effects associated with the time delay introduced by delay circuitry of the feedback loop. This ΣΔ ADC includes a first summing stage, first integrator, second summing stage, second integrator, quantizer, and feedback loop. The second integrator has associated with it a feed forward pass operable to reduce negative effects of delay circuitry within the feed back loop. Feedback loop includes delay circuitry and a number of digital to analog converters. The feed forward path that reduces the effects of the delay includes a resistance within the second or additional integrator. This allows the adverse effects of the time delays associated, which may lead to circuit instability or meta-stability, to be reduced or eliminated.
1. A sigma delta (ΣΔ) analog to digital converter (ADC), comprising:
a first summing stage operable to receive an analog signal;
a first integrator;
at least one additional summing stage operable to receive an output from the first integrator;
at least one additional integrator having a fed forward path, the feed forward path operable to reduce effects of delay circuitry within a feedback loop;
a quantizer; and
the feedback loop comprising:
the delay circuitry, wherein the delay circuitry produces a time delay during which digital processing occurs; and
a plurality of digital to analog converters (DACs) operable to provide digital feedback signals to the summing stages.
2. The ΣΔ ADC of claim 1 , wherein the feed forward path comprises a resistance within the at least one additional integrator.
3. The ΣΔ ADC of claim 2 , wherein the resistance and a capacitance in the feed forward loop establish a time constant associated with the feed forward loop.
4. The ΣΔ ADC of claim 1 , wherein the delay circuitry comprises a latch.
5. The ΣΔ ADC of claim 1 , wherein the delay circuitry provides a fixed delay, and wherein this fixed delay is less than or equal to one clock period.
6. The ΣΔ ADC of claim 5 , wherein this fixed delay is ½ clock period.
7. A method to compensate for a time delay within a feedback loop of a sigma delta (ΣΔ) analog to digital converter (ADC), the method comprising:
receiving an analog signal and a first digital feedback signal;
providing a difference between the analog signal and the first digital feedback signal to a first integrator;
producing an output signal with the first integrator;
providing a difference between the output signal of the first integrator and a second digital feedback signal to a second integrator;
producing an output signal with the second integrator;
feeding forward a zero to compensate for timing delays in the feedback loop that produces the first digital feedback signal and second digital feedback signal;
producing a digital output signal based on the output signal of the second integrator and the fed forward zero; and
producing the first digital feedback signal and second digital feedback signal based on the digital output signal.
8. The method of claim 7 , wherein the feed forward path comprises a resistance within the second integrator.
9. The method of claim 8 , wherein the resistance and a capacitance in the feed forward loop establish a time constant associated with the feed forward loop.
10. The method of claim 7 , where in the timing delay is produced with a latch.
11. The method of claim 7 , wherein the timing delay comprises a fixed delay, and wherein this fixed delay is less than or equal to one clock period.
12. The method of claim 11 , wherein this fixed delay is ½ clock period.
13. A sigma delta (ΣΔ) analog to digital converter (ADC), comprising:
a first summing stage operable to receive an analog signal;
a first integrator;
a second summing stage operable to receive an output from the first integrator;
a second integrator having a feed forward path, the feed forward path operable to reduce effects of delay circuitry within a feedback loop;
a quantizer; and
the feedback loop comprising:
the delay circuitry, wherein the delay circuitry produces a time delay during which digital processing occurs; and
a plurality of digital to analog converters (DACs) operable to provide digital feedback signals to the summing stages.
14. The ΣΔ ADC of claim 13 , wherein the feed forward path comprises a resistance within the at least one additional integrator.
15. The ΣΔ ADC of claim 14 , wherein the resistance and a capacitance in the feed forward loop establish a time constant associated with the feed forward loop.
16. The ΣΔ ADC of claim 13 , wherein the delay circuitry comprises a latch.
17. The ΣΔ ADC of claim 13 , wherein the delay circuitry provides a fixed delay, and wherein this fixed delay is less than or equal to one clock period.
18. The ΣΔ ADC of claim 17 , wherein this fixed delay is ½ clock period.