Memory erase management system
View Patent ↗A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell.
1. A memory erase management method comprising:
providing a resistive change memory cell;
coupling a first line to the resistive change memory cell;
coupling a line buffer to the first line;
providing a charge storage device coupled to the line buffer; and
performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell.
2. The method as claimed in claim 1 further comprising providing a voltage source for charging the charge storage device.
3. The method as claimed in claim 1 further comprising:
providing a read circuit for reading a resistance from the resistive change memory cell;
charging the charge storage device to a voltage indicated by the resistance read; and
enabling a cell transistor by a second line includes discharging the current from the charge storage device through the resistive change memory cell.
4. The method as claimed in claim 1 wherein performing the single pulse erase on the resistive change memory cell is of a predetermined duration.
5. The method as claimed in claim 1 further comprising:
forming a memory system utilizing the memory erase management system; and
forming an integrated circuit or an electronic assembly with the memory system.
6. A memory erase management method comprising:
providing a resistive change memory cell, having a switch cell and a cell transistor;
coupling a bit line to the resistive change memory cell, including a bit line select transistor;
coupling a line buffer to the bit line;
providing a charge storage device coupled to the line buffer, includes providing a capacitor; and
performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell, including passing the current through the cell transistor.
7. The method as claimed in claim 6 further comprising providing a voltage source for charging the charge storage device, in which providing the voltage source includes supplying a variable voltage.
8. The method as claimed in claim 6 further comprising:
providing a read circuit for reading a resistance from the resistive change memory cell, includes determining the programmed resistance value;
charging the charge storage device to a voltage indicated by the resistance read includes determining the current needed to change the resistance of the resistive change memory cell; and
enabling the cell transistor by a word line including discharging the current from the charge storage device through the resistive change memory cell for elevating a temperature in the switch cell.
9. The method as claimed in claim 6 wherein performing the single pulse erase on the resistive change memory cell is in the range of 10-50 nanoseconds in duration, including activating the line buffer.
10. The method as claimed in claim 6 wherein performing the single pulse erase includes elevating a temperature in the resistive change memory cell, including reducing a voltage during the single pulse erase.
11. A memory erase management system comprising:
a resistive change memory cell;
a first line coupled to the resistive change memory cell;
a line buffer coupled to the first line;
a charge storage device coupled to the line buffer in which the charge storage device having a current discharged through the resistive change memory cell in a single pulse erase of the resistive change memory cell.
12. The system as claimed in claim 11 further comprising a voltage source for charging the charge storage device.
13. The system as claimed in claim 11 further comprising:
a read circuit for reading a resistance from the resistive change memory cell; and
a cell transistor enabled by a second line with the current from the charge storage device discharged through the resistive change memory cell.
14. The system as claimed in claim 11 wherein the resistive change memory cell is for performing a single pulse erase in a predetermined duration.
15. The system as claimed in claim 11 further comprising:
a memory system with the memory erase management system; and
an integrated circuit or an electronic assembly with the memory system.
16. The system as claimed in claim 11 wherein:
the resistive change memory cell having a switch cell and a cell transistor, and
the cell transistor passes the current from the charge storage device;
further comprising:
a bit line select transistor coupled to the bit line; and
a capacitor coupled to the line buffer.
17. The system as claimed in claim 16 further comprising a voltage source for charging the charge storage device, in which the voltage source includes a variable voltage supply.
18. The system as claimed in claim 16 further comprising:
a read circuit for reading a resistance from the resistive change memory cell, includes the programmed resistance value determined; and
a word line for enabling the cell transistor with the current from the charge storage device discharged through the resistive change memory cell provides the switch cell having a temperature elevated.
19. The system as claimed in claim 16 wherein the switch cell in the resistive change memory cell changes states in the range of 10-50 nanoseconds in duration, includes the line buffer activated.
20. The system as claimed in claim 16 wherein the resistive change memory cell having the current from the charge storage device discharged through the resistive change memory cell for a temperature elevated, with a voltage reduced during the single pulse erase.