Analog to digital converter with dynamic power configuration
View Patent ↗In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption.
1. An analog to digital converter (ADC) having a dynamic power circuit, comprising:
a track-and-hold circuit having an output and a track mode;
a comparator having an input; and
a preamplifier coupled between said track-and-hold output and said comparator input,
wherein at least one of a preamplifier current and a comparator current are limited during said track mode to reduce ADC power consumption.
2. The ADC of claim 1 , further comprising a transistor coupled between a power source and at least one of a preamplifier output and a comparator output, wherein said transistor conducts during said track mode.
3. The ADC of claim 2 , further comprising a control circuit coupled between said track-and-hold circuit and said transistor.
4. The ADC of claim 1 , further comprising a current control transistor coupled between ground and said preamplifier, wherein said current control transistor resists current flow during said track mode.
5. The ADC of claim 4 , further comprising:
a second transistor coupled between a node and a first voltage source;
a third transistor coupled between said node and a second voltage source,
wherein said node is coupled to control said current control transistor; and
an inverter, wherein an inverter input is coupled to control said second transistor and an inverter output is coupled to control said third transistor.
6. The ADC of claim 1 , further comprising a current control transistor coupled between ground and said comparator, wherein said transistor resists current flow during said track mode.
7. The ADC of claim 1 , further comprising:
a second transistor coupled between a node and a first voltage source;
a third transistor coupled between said node and a second voltage source,
wherein said node is coupled to control said current control transistor; and
an inverter, wherein an inverter input is coupled to control said second transistor and an inverter output is coupled to control said third transistor.
8. The ADC of claim 1 , further comprising:
a latch circuit coupled to a comparator output; and
a transistor coupled between said latch circuit and a comparator input,
wherein said transistor is controlled during said track mode to reduce said comparator current.
9. The ADC of claim 1 , wherein at least one of said track-and-hold circuit, said preamplifier, and said comparator are deposited on a substrate.
10. A method for reducing power consumption in an analog-to-digital converter (ADC) having a track-and-hold circuit coupled to a comparator via a preamplifier, wherein the preamplifier has a load, comprising:
determining a track mode of the track-and-hold circuit;
developing a control signal based on said determining; and
adjusting a current flow in the ADC to reduce ADC power consumption,
wherein said control signal controls said adjusting.
11. The method of claim 10 , wherein said adjusting further comprises at least one of selectively coupling resistance to vary the load, shorting the load, and limiting a differential pair current flow.
12. The method of claim 11 , further comprising selecting a transistor control voltage with said control signal.
13. The method of claim 11 , further comprising inverting said control signal to select said transistor control voltage from a plurality of voltages.
14. The method of claim 11 , wherein said current flow is reduced in the comparator or the preamplifier.
15. An analog to digital converter (ADC), comprising:
means for determining a track mode of a track-and-hold circuit; and
means for developing a control signal based on said determining means,
means for adjusting a current flow in the ADC to reduce ADC power consumption, wherein said control signal controls said adjusting means.
16. The ADC of claim 15 , wherein said adjusting means further comprises at least one of means for selectively coupling resistance to vary a load, means for shorting said load, and means for limiting a differential pair current flow.
17. The ADC of claim 15 , further comprising means for suppressing reference ladder noise during said track mode.
18. The ADC of claim 17 , further comprising means for selecting a transistor control voltage with said control signal.
19. The ADC of claim 15 , wherein said current flow is reduced in at least one of a comparator and a preamplifier.
20. The ADC of claim 15 , further comprising means for resetting at least one of a preamplifier and a comparator based on said control signal.