SRAM test method and SRAM test arrangement to detect weak cells
View Patent ↗A method and a test arrangement for testing an SRAM having a first cell and a second cell coupled between a pair of bitlines is disclosed. In a first step, a data value is stored in the first cell being the cell under test (CUT), and its complement is stored in a second cell, being the reference cell. Next, the bitlines are precharged to a predefined voltage. Subsequently, the wordline of the reference cell is enabled for a predefined time period, for instance by providing the wordline with a number of voltage pulses. This causes a drop in voltage of the bitline coupled to the logic ‘0’ node of the reference cell. In a subsequent step, the wordline of the CUT is enabled, which exposes the CUT to the bitline with the reduced voltage. This is equivalent to weakly overwriting the CUT. Finally, the data value in the CUT is evaluated. If the data value has flipped, the CUT is a weak cell. Cells with varying levels of weakness can be detected by varying the reduced voltage on the aforementioned bitline.
1. A method for testing a static random access memory having a first cell and a second cell coupled between a first bitline and a second bitline, the first cell being responsive to a first wordline and the second cell being responsive to a second wordline, the method comprising:
testing the first cell, the testing the first cell comprising:
storing a data value in the first cell;
storing the complement of the data value in the second cell;
charging at least one of the first bitline and the second bitline to a predefined voltage;
enabling the second wordline for a predefined time period after the complement of the data value has been stored in the second cell;
enabling the first wordline; and
evaluating the data value stored in the first cell.
2. The method of claim 1 , wherein enabling the second wordline for a predefined time period comprises providing the second wordline with N voltage pulses having a combined pulse width corresponding to the predefined time period, with N being an integer and being at least 2.
3. The method of claim 2 , further comprising selecting a value of N.
4. The method of claim 2 , comprising defining the pulse width.
5. The method of claim 1 , further comprising:
storing a further data value in the first cell;
storing the complement of the further data value in the second cell;
charging at least one of the first bitline and the second bitline to a further predefined voltage;
enabling the second wordline for a further predefined time period; enabling the first wordline; and
evaluating the further data value stored in the first cell.
6. The method of claim 1 , further comprising:
storing a second further data value in the first cell;
storing the complement of the data value in the second cell;
charging at least one of the first bitline and the second bitline to a predefined voltage;
enabling the first wordline for a predefined time period; enabling the second wordline; and
evaluating the data value stored in the second cell.
7. A test arrangement for testing a static random access memory having a first cell and a second cell coupled between a first bitline and a second bitline, the first cell being responsive to a first word line and the second cell being responsive to a second wordline, the test arrangement comprising:
means for testinci the first cell, the means for testing the first cell comprising:
means for storing a data value in the first cell;
means for storing the complement of the data value in the second cell;
means for charging at least one of the first bitline and the second bitline to a predefined voltage;
means for enabling the second word line for a predefined time period after the complement of the data value has been stored in the second cell;
means for enabling the first word line; and
means for evaluating the data value in the first cell.
8. The test arrangement of claim 7 , wherein the means for enabling the wordline of the second cell for a predefined time period comprise means for providing the second wordline with N voltage pulses having a combined pulse width corresponding to the predefined time period, with N being an integer and being at least 2.
9. The test arrangement of claim 8 , wherein N is configurable.
10. The test arrangement of claim 8 , wherein the pulse width is configurable.
11. The test arrangement of claim 7 , wherein the test arrangement is integrated in the static random access memory.